Design and Simulation of Binary to BCD Conversion

Ankit Kumar Gupta, 2Monika Mangla Department of Electronics & Communication 1&2 I.E.T College, Alwar (Rajasthan) 1 ankitkgupta09@gmail.com , 2er.monika.mangla09@gmail.com
1&2 1

Abstract Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Binary to BCD conversion forms the basic building block of decimal digit multipliers. This paper presents a high speed, low power architecture for fixed bit binary to BCD conversion which is better in terms of power-delay. Keywords-BCD conversion, BCD number system, Binary number system ,FPGA, VHDL.

I. INTRODUCTION
Decimal arithmetic operations are generally slow and complex, its hardware occupies more area. They are typically implemented using iterative approaches or lookup table based reduction schemes. This has led to the motivation behind improving BCD architectures, to enable faster and compact arithmetic.The rest of this paper is organized as follows: Section 2 gives an overview on BCD and binary number system. Section 3 gives an overview on binary to BCD conversion. Section 4 gives an overview on advantage of BCD number system. Section 5 contains simulation and result. Section 6 contain conclusion. Section 7- contain reference.

(10010011 0010 0001) BCD. It can be seen that each digit of the decimalnumber is coded in binary and then concatenated to form the BCDrepresentation of the decimal number. As any BCD digit lies between [0, 9] or [0000, 1001], multiplying two BCD digits can result in numbers between [0, 81]. All the possible combinations canbe represented in a 7-bit binary number when multiplied, (81)10 or (1010001)2 being the highest. In BCD multiplication where 4-bit binary multipliers are used to multiply two BCD numbers X and Y with digits, Xi and Yj, respectively, a partial product Pij is generated of the form (p6p5p4p3p2p1p0)2. Conversion of Pij from binary to a BCD number BiCj where (Xi, Yj) = 10Bi + Cj needs fast and efficient BCD converters. The binary to BCD conversion is generally can be done in parallel for every partial product after each BCD digitis multiplied as shown in Figure 1 and the resulting BCD numbers after conversion can be added using BCD adders. Another alternative would be to compress the partial products of all binary terms in parallel and then convert them to BCD as done in [8]. The decimal equivalent of BCD Number 0001 1001 0000 0111 is 1907. APPLICATION OF BCD NUMBER SYSTEM:-BCD numbers are useful wherever decimal information is transferred into Or out of a digital system. The circuits inside pocket calculators, for example, can process BCD numbers because we enter decimal numbers through the keyboard and see decimal answers on LED or liquid crystal display.Other examples of BCD systems are electronic counters, digital voltmeters and digital clocks; their circuits can work with BCD numbers.

II.BCD AND BINARY NUMBER SYSTEM

BINARY NUMBER SYSTEM:-The binary number system also called the base-2 number system is a method of representing number that count by using combination : zero (0) and one(1). Computer use the binary number system to manipulate and store all of their data include numbers , word , video, graphics and music. The first binary number system was documented by Gottfried Leibniz in the 17th century. In 1854 mathematician George Boole came up with a system of logic that is know today as Boolean Algebra (based on two elements 0's and 1's).The term bit the smallest unit of digital technology stands for binary digit a byte is a group of eight bit . a kilobyte is 1,024 bytes or 8,192 bits.The binary number system is similar to the decimal system, with two important differences. First, the multipliers starting with the least significant digit and moving to the left are consecutively higher powers of 2: 2 (or 21), 4 (or 22), 8 (or 23), etc. 1 (or 2),The second difference is that any digit position may contain only a 0 or 1, whereas, in the decimal system, any digit position may contain 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9. An example of a binary number, then, isMultipliers. In binary system, the number (125) is represented as 1111101 meaning 1*26 +1* 25 +1* 24 +1*23 +1* 22 +0* 21 +1*2 0 BCD NUMBER SYSTEM:- Meaning of BCD "Binary Coded Decimal", is a method that use binary digits 0 which represent off and 1 which represent on. BCD has been in use since the first UNIVAC computer. Each digit is called a bit. Four bits are called a nibble and is used to represent each decimal digit (0 through 9).The digital value appears on the converters output as a binary or binary coded decimal (BCD). The value is obtained by dividing the sampled analog input voltage [ David G. Morrison Oct 13, 2003 ] BCD numbers are useful wherever decimal information is transferred into a computer.BCD is a decimal representation of a number directly coded inbinary, digit by digit. For example, the number (9321)10 =

III. BINARY TO BCD CONVERSION

Binary-to-BCD conversion is performed in a modified shift register that successively doubles its BCD contents. The binary data is shifted into the converter serially, MSB first. Subsequent bits are entered into the shift register to fill the LSB vacated by the doubling. The conversion is complete when all bits of the binary input have been entered, at which time the BCD result is available in parallel form. Each input bit will have been doubled and redoubled to regain its original binary weight, but in BCD format. To remain a valid BCD number when doubled, a BCD digit of 5 or greater must not just be shifted, but must be converted into the proper BCD representation of its doubled value; along with a 1 being shifted into the next higher digit, a 5 is converted into a 0, a 6 into a 2, a 7 into a 4, an 8 into a 6, and a 9 into an 8. The binary-to-BCD converter requires three CLBs for each BCD digit in the output. To start a new conversion, INIT should be asserted at the time the binary MSB is applied to the converter input. INIT clears all bits except the LSB which is loaded.

Table-1: Binary to BCD conversion

Serial No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Integer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Binary to BCD conversion Binary BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 00010000 00010001 00010010 00010011 00010100 00010101

(v).Many non-integral values, such as decimal 0.2, have an infinite place-value representation in binary (.001100110011...) but have a finite place-value in binary-coded decimal (0.0010) .Consequently a system based on binary-coded decimal representations of decimal fractions avoids errors representing and calculating such values.

V. SIMULATION AND RESULT

All the architectures have been described using VHDL. Delay, power and area values for the designs are obtained by synthesizing the VHDL description. The inputs are given at a clock frequency of 350 MHz. The architectures are simulated for all the possible conversion cases and results are shown in below Minimum period: Maximum Frequency: Minimum input arrival time before clock: Maximum output required time after clock: 13.980ns 71.531MHz 9.536ns 7.999ns

Timing constraint: Default period analysis for Clock 'clk' Delay: 13.980ns (Levels of Logic = 5) Source: signal_count_8 (FF) Destination: signal_temp_10 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: signal_count_8 to signal_temp_10 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FD:C->Q 3 1.292 1.480 signal_count_8 (signal_count_8) LUT4_D:I0->O 4 0.653 1.600 Mcompar__n0009_inst_lut4_21 (Mcompar__n0009_inst_lut4_2) LUT2_D:I0->O 1 0.653 1.150 _n003758 (CHOICE194) LUT4:I2->O 5 0.653 1.740 _n0037176 (_n0037) LUT4_D:I1->O 15 0.653 2.700 Ker44631 (N4465) LUT2_L:I0->LO 1 0.653 0.000 _n0019<9>1 (N6134) FDS:D 0.753 signal_temp_9 ---------------------------------------Total 13.980ns (5.310ns logic, 8.670ns route) (38.0% logic, 62.0)%route ------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 9.536ns (Levels of Logic = 4) Source: reset (PAD) Destination: signal_temp_10 (FF) Destination Clock: clk rising Data Path: reset to signal_temp_10 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 4 0.924 1.600 reset_IBUF (reset_IBUF) LUT2:I1->O 4 0.653 1.600 Ker4568_SW0 (N5328) LUT4_D:I0->O 15 0.653 2.700 Ker44631 (N4465) LUT2_L:I0->LO 1 0.653 0.000 _n0019<9>1 (N6134) FDS:D 0.753 signal_temp_9 ---------------------------------------Total 9.536ns (3.636ns logic, 5.900ns route) (38.1% logic, 61.9% route) -------------------------------------------------------------------------

EXAMPLE (1)Binary number Integer number BCD number EXAMPLE (2)Binary number Integer number BCD number .

( 010010111111)2 (1)10 (2)10 (1)10 (0001)2 (0010)2 (0001)2 (0001001000010101)BCD (111111111111)2 (4)10 (0)10 (9)10 (0100)2 (0000)2 (1001)2 (0100000010010101)BCD

(5)10 (0101)2

(5)10 (0101)2

IV. ADVANTAGES OF BCD OVER BINARY NUMBER SYSTEM

(i). One advantage of BCD over binary representations is that there is no limit to the size of a number. To add another digit, just add a new 4bit sequence. (ii).Numbers represented in pure binary format are limited to the largest number that can be represented by 8, 16, 32 or 64 bits. Sometimes, the right-most nibble contains the sign (positive or negative). (iii). It is easier to convert decimal numbers to and from BCD than binary and, though BCD is often converted to binary for arithmetic processing, it is possible to build hardware that operates directly on BCD. (iv).In terms of multiplication improvement of 15.135% in terms of delay and is 15.769% better in terms of power giving it a 28.52% improvement in terms of power delay product over the most efficient architecture .

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 7.999ns (Levels of Logic = 1) Source: bcd_15 (FF) Destination: bcd<15> (PAD) Source Clock: clk rising Data Path: bcd_15 to bcd<15> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDE:C->Q 1 1.292 1.150 bcd_15 (bcd_15) OBUF:I->O 5.557 bcd_15_OBUF (bcd<15>) ---------------------------------------Total 7.999ns (6.849ns logic, 1.150ns route) (85.6% logic, 14.4% route)

Fig 4:- RTL Schematic of binary to BCD conversion

Fig. 1 simulation result of binary to BCD conversion

Fig 5:- RTL Schematic Fig 2 Rtl view of binary to BCD conversion

Fig 3:- RTL Schematic

Fig 8:- RTL Schematic

VI. CONCLUSION
The proposed binary to BCD conversion has been calculated by using Xilinx software. After the simulation and analysis we have seen that this circuit gives low power and high speed architecture which is shown in figures.

Fig 6:- RTL Schematic

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VII. REFRENCE

Fig 7:- RTL Schematic