I2C Bus -- Specification An Understanding approach

I2C Bus Inter IC Bus

Features Only two bus lines are required

-- Serial Data Line(SDA)

-- Serial Clock Line(SCL)

True multi-master bus including collision detection and arbitration. Serial, 8-bit oriented, bi-directional data transfer 100 kbit/s(SM), 400Kbit/s(FM), 3.4 Mbit/s(HS)

Features Contd ..

Both SDA & SCL are open collector Inputs/Outputs

On-chip filtering rejects spikes on data bus (data integrity)

Device connected to bus software addressable unique Master/Slave Relationship Master can be a transmitter or Receiver

Features Contd., The data is clocked along with a clock signal(SCL) The clock signal controls when the data is to be changed and when it should be read Since I2C is synchronous, the clock rate can vary l

 The Master device controls the clock (SCL)

No data is transferred unless a clock signal is present

All slaves are controlled by the master clock

SDA Serial Data, SCL Serial CLock

In Normal Conditions,SDA Never changes when SCL is High (Data is valid during high period of Clock only)

I2C Signals Signal Levels :a) Float High (logic 1) b) Drive Low (logic 0)

I2C Pull-up Resistor Setting Suggestions

I2C Frame Details S Address A

S\Start
S\Address S\Acknowledge DataS

Data
P Rs

SRRepeat - Start

Data Transfer on the I2C Bus

ACK ref.Clk Pulse is generated by the master

9th Clock

Acknowledge on the I2C Bus

A receiver which was being addressed has to generate an ACK after each byte has been received

When a slave doesnt acknowledge the slave address,then data lines must be left HIGH by the Slave Then Master decides whether to generate a STOP condn or repeated Start to start a new transfer

Master Receiver,Slave - Transmitter

If a master receiver is involved in a transfer,it must signal the end of data to the slave-transmitter

By not generating an ACK on the last byte,then slave

transmitter must release the data line to allow the mster to generate a STOP or REPEATED START

Clock synchronizaton

 Clock Sync. Is performed using Wired-And Technology When SCL moves from high to low,the devices start counts their
low period.

ARBITRATION

When two Masters tries to gain the access of I2C bus,then..

If a master also incorporates a slave function and it loses

arbitration during the addressing stage, its possible that

the winning master is trying to address it. The losing master must therefore switch over immediately to its slave

mode.

SPI

I2C

1. Three bus lines are required; 1. Two bus lines are required; SDA, SCL. MOSI,MISO,SCK, & SS.
2. No official specification (Component dependent) 3. Higher data rates ( up to 10 MHz or more) 4. More efficient in point-topoint (Single master, Single slave) applications. 2. With official specification. (I2C protocol created by philips.) 3. Support transfer speeds of around 100 kHz ( original standard , or 400 kHz using the most recent standard) 4. More efficient in multimaster, multi-slave applications.

SPI
5. Lack of built-in device addressing.
6. Does not have an acknowledgement mechanism to confirm receipt of data. 7. Less overhead when handling point-to-point application.

I2C
5. Built-in addressing scheme and straightforward.
6. Have an acknowledgement mechanism to confirm receipt of data. 7. More overhead when handling point-to-point application.

8. Suited better for communications with on8. Suited better for applications board devices that are that are naturally thought of accessed on an occasional as data stream.