Microprocessor History

Early microprocessors
PMOS technology slow and awkward to interface with TTL family 4 bit processor Instructions were executed in about 20 s. Intel 4004 the first MP. 4K nibbles address space. Intel 8008- can manipulate a whole byte. 16Kbytes address space 50,000 operations/second.

N-channel MOSFET
1970. Faster than P-MOS. Work with +ve supply; easy to interface with TTL. 1973 Intel 8080 MP. 500,000 operations/second. 64K bytes memory. Upward software compatible with 8008. Other brands are MC6800, Fairchilds F-8 etc.

Basic types of MP
Two types
Single component microprocessors Bit sliced microprocessors
Can be cascaded to allow functioning systems with word size from 4 bits to 200 bits.

Single component M Computer

Composed of
A processor read only memory (for program storage) Read/Write memory (for data storage) Input/output connections for interfacing Timer as event counter

Intel 8048, Motorola 6805R2.

Oven, washing machine, dish washer etc.

Modern MP
8, 16, 32, 64 bits are available. Intel 8085, Motorola 6800 8 bit word 16 bit address. Intel 8088, 8086, Motorola 68000 16 bits word, 20 bits address. 80186 never used. 286 real mode and protected mode; 16MB memory 386 paging, 4GB memory, 32 bits word 486 math coprocessor, L1 cache

Modern MP
Pentium
64 bits i/o off the chip but process 32bits word, exception floating point processed 64 bits, cache doubled, instruction pipelining.

Pentium Pro
L2 cache, Improved pipelining

Pentium MMX
Multi-Media extensions, 57 new inter instruc mostly used for multimedia programming

Pentium II, III, IV

Pentium pro with MMX tech, increased L2 cache, full 64 bit operation

RISC
Reduced instruction set processor, uniform length instruc, faster in operation, cannot perform may different thing as CISC.

Basic MP architecture
Fetch, decode, execute. PC increment. First instruction is a fetch
0000H for 8085 FFFF0H for 8086, 8088
Data Bus AF, BC, DE, HL, SP, PC many more Register Array

Instruction Register

ALU

Control Bus control Address Bus

Memory Interfacing and IO decoding

 Interfacing needs bus Isolation and separation of signals from different devices connected to MP.
Unidirectional Bidirectional

LS373, 244

Memory map
Pictorial representation of the whole range of memory address space.
Defines which memory system is where, their sizes etc.

Address space or range.

8086 has 1M address space in minimum mode. 8085 has 64K address sspace.

Address Decoding
Address decoder is a digital ckt that indicates that a particular area of memory is being addressed, or pointed to, by the MP. Absolute address decoding
Decode an address to one single output Decode 10110 so that u can get a signal from the decoder when it receives exactly that bit pattern.

Partial address decoding

Some bits are used as dont care so that decoder gives a signal for a range of consecutive bit patterns.

Absolute decoding
10110 abcde 10 11 0 0

abcde

Active low o/p signal

Can use decoder IC with gates to achieve exact decoded o/p

3 to 8 line dcd

1 0 1

o/p 7 Logic 1 8 input NAND gate implementation

Partial decoding
When a range of addresses are deconded then it is called partial decoding. For example, if we need to generate a control signal for an address generated by the MP within the range FFF0 FFFF, then it is called partial decoding.
1111 1111 1111 xxxx A15 A14

A4

Decoder, multiplexer can be used for address decoding

Internal architecture of 8085

ALU

Flag register
S Z AC P CY 1. S : after the execution of an arithmetic operation, if bit 7 of the result is 1, then sign flag is set. 2. Z : bit is set if ALU operation results a zero in the Acc or registers. 3. AC: bit is set, when a carry is generated by bit 3 and passed on bit 4. 4. P: parity bit is set when the result has even number of 1s. 5. CY = carry is set when result generates a carry. Also a borrow flag.

Accumulator
Hold data for manipulation (arithmetic, logical). Whenever the operation combines two words, either arithmetically or logically, the accumulator contains one word (say A) and the other word(say B) may be contained in a register or in memory location. After the operation the result is placed in the Acc replacing the word A. Major working register. MP can directly work on Acc. Programmed data tranfer.

General purpose registers

Six registers. B, C, D, E, H and L can store 8 bit data. They can be combined to perform some 16 bit operation.

ALU
Arithmetic logic unit. Two input ports, one output port. Perform AND, OR, ExOR, Add, subtract, complement, Increment, Decrement, shift left, shift right. ALUs two temporary registers are connected to MPs internal bus from which it can take data from any registers. It can place data directly to data bus through its single output port.

Program counter
Its job is to keep track of what instruction is being used and what the next instruction will be. For 8085 it is 16 bit long. Can get data from internal bus as well as memory location. PC automatically increments to point to the next memory during the execution of the present instruction. PC value can be changed by some instructions.

Stack pointer
16 bit register acts as memory pointer. Can save the value of the program counter for later use. points to a region of memory which is called stack. follows LIFO algorithm. After every stack operation SP points to next available location of the stack. Usually decrements.

Memory address register

PC sends address to MAR. MAR points to the location of the memory where the content is to be fetched from. PC increments but MAR does not. If the content is an instruction, IR decodes it. During execution if it is required to fetch another word from memory, PC is loaded with the value PC again sends it to the MAR and fetch operation starts.

Instruction register
Holds instruction the micro is currently being executed. 8 bit long.

others
Instruction decoder. Control logic. Internal data bus.

8085
40 pin DIP. +5V 3 - 5MHz
ADD BUS DATA BUS CONTROL STATUS POWER SUPPLY AND FREQ EXTERNALLY INITIATED SIGNALS SERIAL I/O PORTS
SID 5 SOD 4 X1 X2

5V

GND

40 20
21 28 HIGH ORDER ADD BUS

TRAP 6 RST7.5 7 RST6.5 8 RST5.5 9 INTR 10 READY 35 HOLD 39

12 19 MUX ADD/ DATA BUS 30 ALE 29 S0 33 S1 34 IO/M 32 RD 3 37 31 WR

RESET IN 36
INTA 11 HLDA 38

RESET OUT

CLK OUT

ADD/DATA bus
Address bus 16 bits
A8 to A15 unidirectional. Higher 8 bit Address bus. higher 8 This pins AD0 to AD7 multiplexed with data. bit are bidirectional when used as data bus. A
A15
8

Data bus 8 bit long: AD0 to AD7

ALE G AD7 AD6 AD5 D Q

Address bus. Lower 8 bit

OC GND

AD0

Data bus

Control signals
ALE active high output used to latch the lower 8 address bits. RD, WR - active low output signals. IO/M output signal to differentiate memory and IO operation. S1 and S0 status output signal. Identify various operations.
Machine cycle Opcode fetch Memory read Memory write I/O read I/O write Interrupt Ackn Halt Hold Reset IO/M 0 0 0 1 1 1 Z Z Z S1 1 1 0 1 0 1 0 X X S0 1 0 1 0 1 1 0 X X Control signals RD=0 RD=0 WR=0 RD=0 WR=0 INTA=0 RD, WR =Z and INTA=1

External control signals

INTR interrupt request. Input signal INTA interrupt acknowledge. o/p signal. RST7.5,RST 6.5, RST5.5 restart interrupts. Vectored interrupts. Higher priority. TRAP - Nonmaskable interrupt. Highest priority. Hold request for the control of buses. O/P signal HLDA Hold Acknowledge. I/P signal READY I/P signal. When low Mp waits for integral number of clock cycles until it goes high.

Bus control signals

MEMR IOWR MEMWR IOWR

IO/M

RD

8085
WR

8080 functional block diagram

Interrupt control Serial I/O control
MUX

Accumu

Temp Reg

Instru Register (8)

Reg Select

Flags

Instru Decoder

W Z Temp Reg (8) Temp Reg (8) B C (8) (8) D E (8) (8) H L (8) (8) Stack pointer (16) Program counter (16) Incrementer/decrementer Latch (16)

Address buffer (8)

Data/Add buffer (8)

Timing & control

Timing diaga. of Memory cycle

T1
T2 T3 CLK A15-A8 T1 T2 T3

A7-A0

Data from memory

AD7-AD0 ALE IO/M RD MEMRD WR MEMWR

A7-A0

Data from MPU

READ Cycle

WRITE Cycle

Interfacing A Memory Chip

2K Byte memory Memory address space of the chip: 8800H to 8FFFH
IO/M A13 A12 A11 A14 A15 E1 E2 E3 3 to 8 decoder Q1 A10 A9

MEMSEL

CE Memory Chip

D7 D6

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 8 0 0 1 X X X X X X X X X X X

A0 RD WR

D0

8-F

0-F

0-F

MVI A,32H Instruction

2000H 2001H 3EH ;MVI A, 32H 32H
M1 (Opcode-fetch) T1 T2 T3 T4 M2 (Memory Read) T1 T2

T3

A15-A8 AD7-AD0 ALE

20H; high-order address

00H; loworder Add

Unspecified

20H; High-order address

3E; opcode

01H; loworder Add

32H; Data

Status IO/M=0,S1=1,S0=1; opcode fetch

Status IO/M=0,S1=1,S0=0; data read

RD

OUT/IN instruction
port address: 50H 2050 D3 OUT 50H sends acc content to I/O address 50H 2051 50 Let input port address is 30H 2150 DB IN 30H reads content from I/O address 30H and 2151 30 stores the value in accum

IN 30H instruction
M1
T1 CLK A15-A8 AD7-AD0 T2 T3 T4 T1

M2
T2 T3 T1

M3
T2 T3

21H
50H
DB from memory

unspec ified

21H

Port add 30H Data from Accumula

51H

Port addre 30H

Port add 30H

ALE IO/M

RD MEMRD IORD

OUT 50H instruction

M1
T1 CLK A15-A8 AD7-AD0 T2 T3 T4 T1

M2
T2 T3 T1

M3
T2 T3

20H
50H
Opcode D3

unspec ified

20H

Port add, 50H Port addre 50H Port add 50H Data from Accumula

51H

ALE

IO/M
RD MEMRD IORD IOWR

Device selection & Data Transfer

Decode the IO address. Combine it with control the signal to generate a unique IO select pulse that is generated only when both signals are asserted. Use it to activate the IO port Address decoding can be absolute or partial

Address lines

Decoder

IOR or IOW

NOR

Latch Or Tri-state Buffer

To Peripherals

Enable

Data bus

Interfacing LED for display

Given port add: FFH Use octal latch as o/p port. Steps for IO select pulse:
Decode FF Use IO/M to make the port output only Use WR signal to write data to the port

MVI A, data OUT FFH HLT * To interface a 7-segment display you need to decide about the type of 7-segment: common anode or common cathode * Power supply connection to the LED segments will be opposite. * For common cathode a 0 is sent to the respective pin to lit it up.

A7 A1 A0

Q7

WR IOSEL
G

IO/M
A10 A9
D FF

+5 V

A0
OE

Interfacing DIP switches

Let port address: 07H 00H Partial decoding Must use pull-up resistors. IN 07H instruction reads a byte into accumulator from port 07H
A4 A7 A6 A5 A3 IO/M Q0 RD E1 E 2 E3 3 to 8 decoder

IOSEL
OE

D7

D1 D0

+5 V