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Paging
Paging
A different approach Addresses all of the issues of previous topic Introduces new issues of its own
Paging
Memory Management
Virtual (or logical) address vs. Physical address
CPU
Logical Addresses
MMU
Physical Addresses
Memory
I/O Devices
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Use fixed size units in both physical and virtual Logical Address Space memory (virtual memory) Provide sufficient MMU page 0 hardware to allow units to be scattered across page 1 memory page 2 Make it possible to leave MMU page 3 infrequently used parts of virtual address space out page X of physical memory Solve internal & external fragmentation problems
physical memory
frame Y
Paging
Processes see a contiguous virtual address space Memory Manager divides the virtual address space into equal sized pieces called pages Memory Manager divides the physical address space into equal sized pieces called frames
Frame size usually a power of 2 between 512 and 8192 bytes Frame table
One entry per frame of physical memory State
Free Allocated to one or more processes
sizeof(page) = sizeof(frame)
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Page tables
Supported by MMU hardware Managed by the Memory Manager Map virtual page numbers to page frame numbers
one page table entry (PTE) per page in virtual address space i.e., one PTE per VPN
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Paging Translation
logical address
virtual page #
offset
physical memory
page frame #
F(PFN)
offset
page frame Y
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PTE Structure
1 1 1 V R M 2 prot 20 page frame number
Paging Advantages
Easy to allocate physical memory
pick any free frame
No external fragmentation
All frames are equal
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Note
Protection bits are important part of paging A process may have valid pages that are
not writable execute only etc.
E.g., setting PTE protection bits to prohibit certain actions is a legitimate way of detecting the first action to that page.
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Questions?
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Observations
Recurring themes in paging
Temporal Locality locations referenced recently tend to be referenced again soon Spatial Locality locations near recent references tend to be referenced soon
Definitions
Working set: The set of pages that a process needs to run without frequent page faults Thrashing: Excessive page faulting due to insufficient frames to support working set
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Paging Issues
#1 Page Tables can consume large amounts of space
If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space -> 4MB for each processs page table What happens for 64-bit logical address spaces?
#2 Performance Impact
Converting virtual to physical address requires multiple operations to access memory
Read Page Table Entry from memory! Get page frame number Construct physical address Assorted protection and valid checks
Without fast hardware support, requires multiple memory accesses and a lot of work per logical address
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Paging
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master page #
secondary page#
offset
physical memory
physical address
page frame #
secondary page table # addr
page frame Y
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12 bits
virtual address
master page #
secondary page#
physical address
page frame #
secondary page table # addr
page frame Y
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Note
Note: Master page number can function as Segment number
previous topic
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Paging Issues
Minor issue internal fragmentation
Memory allocation in units of pages (also file allocation!)
#2 Performance Impact
Converting virtual to physical address requires multiple operations to access memory
Read Page Table Entry from memory! Get page frame number Construct physical address Assorted protection and valid checks
Without fast hardware, requires multiple memory accesses and a lot of work per logical address
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Associative Memory
(aka Dynamic Address Translation DAT)
VPN # Frame #
Do fast hardware search of all entries in parallel for VPN If present, use page frame number (PFN) directly If not,
a) Look up in page table (multiple accesses) b) Load VPN and PFN into Associative Memory (throwing out another entry as needed)
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Bridge
I/O device
I/O device
I/O device
I/O device
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TLB-related Policies
OS must ensure that TLB and page tables are consistent
When OS changes bits (e.g. protection) in PTE, it must invalidate TLB copy If dirty bit is set in TLB, write it back to page table entry
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I.e., use the file for swap space for that part of VM
Access to X + n refers to file at offset n All mapped file PTEs marked at start as invalid OS reads from file on first access OS writes to file when page is dirty and page is evicted
Observation
A great idea when used correctly No substitute for structured input & output of applications
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Paging Summary
Partition virtual memory into equal size units called pages Any page can fit into any frame in physical memory No relocation in virtual memory needed by loader Only active pages in physical memory at any time Supports very large virtual memories and segmentation Hardware assistance is essential An dual instance of the fundamental principle of caching
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Definition Cache
A small subset of active items held in fast storage while most of the items are in much larger, slower storage
Virtual Memory
Very large, mostly stored on (slow) disk Small working set in (fast) RAM during execution
Page tables
Very large, mostly stored in (slow) RAM Small working set stored in (fast) TLB registers
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Program execution
Keep the bytes near the current program counter in on-chip memory while rest of program is in RAM
File management
Keep disk maps of open files in RAM while retaining maps of all files on disk
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Caching issues
When to put something in the cache What to throw out to create cache space for new items How to keep cached item and stored item in sync after one or the other is updated How to keep multiple caches in sync across processors or machines Size of cache needed to be effective Size of cache items for efficiency
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Homework Assignment
Read (for next week)
Silbershatz, Chapter 8 and 9.1 9.3
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Break
Next Topic
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