Microprocessor And Microcomputer

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INTRO TO MMX TECHNOLOGY

MMX (multimedia extensions) technology adds 57 new instructions to the instruction set of the PentiumP4 microprocessors.
also new general-purpose instructions

The new instructions are designed for applications such as motion video, combined graphics with video, image processing, audio synthesis, speech synthesis and compression, telephony, video conferencing, 2D graphics, and 3D graphics.

Data Types
MMX architecture new packed data types:
eight packed, consecutive 8-bit bytes four packed, consecutive 16-bit words two packed, consecutive 32-bit doublewords

Bytes in this multibyte form have consecutive memory addresses and use the little endian form, as with other Intel data. See Figure 1 for the format for these new data types.

Figure 1 The structure of data stored in the MMX registers.

 MMX technology registers have the same format as a 64-bit quantity in memory and have two data access modes:
64-bit access mode, for 64-bit memory and registers transfers for most instructions 32-bit access mode for 32-bit memory and register transfers for most instructions

32-bit transfers occur between processor registers. 64-bit transfers occur between floating-point coprocessor registers.

 Fig 2 shows the internal register set of MMX technology extensions and how it uses the floating-point coprocessor register set.
called aliasing because the floating-point registers are shared as the MMX registers

MMX registers (MM0MM7) are the same as the floating-point registers.

the MMX register set is 64 bits wide and uses the rightmost 64 bits of the floatingpoint register set

Figure 2 The structure of the MMX register set. Note that MM0 and FF0 through MM7 and FP7 interchange with each other.

Instruction Set
The instruction for MMX technology includes arithmetic, comparison, conversion, logical, shift, and data transfer instructions. The instruction types are similar to the microprocessors instruction set.
MMX instructions use data types shown in Fig 1 instead of the normal data types used with the microprocessor

Arithmetic Instructions
Addition, subtraction, multiplication, a special multiplication with an addition, and others. PADD and PSUB instructions add or subtract packed signed or unsigned packed bytes, packed words, or packed doubleword data.
the add instructions are appended by B, W, or D to select size, as in PADDB for a byte, PADDW for a word, and PADDD for a doubleword

The same is true for the PSUB instruction.

 PMULHW & PMULLW perform multiplication on four pairs of 16-bit operands, producing 32-bit results.
PMULHW multiplies the high-order 16 bits PMULLW multiplies the low-order 16 bits

PMADDWD multiplies and adds.

after multiplying, the four 32-bit results are added to produce two 32-bit doubleword results

The MMX instructions use operands just as the integer or floating-point instructions do.

Comparison Instructions
There are two comparison instructions:
PCMPEQ (equal) & PCMPGT (greater than)

There are three versions of each instruction:

PCMPEQUB (compares bytes) PCMPEQUW (compares words) PCMPEQUD (compares doublewords)

These instructions do not change processor flag bits

the result is all ones for a true condition all zeros for a false condition.

Conversion Instructions
Two basic conversion instructions: PACK, available as PACKSS (signed saturation) and PACKUS (unsigned saturation). PUNPCK, available as PUNPCKH (unpack high data) and PUNPCKL (unpack low data) Appended with B, W, or D for byte, word, and doubleword pack and unpack.
but must be used in combinations WB (word to byte) or DW (doubleword to word)

Logic Instructions
PAND (AND) PANDN (NAND) POR (OR) PXOR (Exclusive-OR). These do not have size extensions & perform bit-wise operations on all 64 bits of the data.

Shift Instruction
Logical shifts and arithmetic shift right instructions. Logic shifts are PSLL (left) and PSRL (right).
variations are word (W), doubleword (D), and quadword (Q)

The PSRA (arithmetic right shift) instruction functions in the same manner as the logical shifts.
except the sign-bit is preserved

Data Transfer Instructions

MOVED and MOVEQ.
allow transfers between registers and between a register and memory

MOVED transfers 32 bits of data between an integer register or memory location and an MMX register. MOVEQ copies all 64 bits of an MMX register between memory or another MMX register.
MOVEQ MM2, MM3 transfers all 64 bits of MM3 into MM2

EMMS Instruction
EMMS (empty MMX-state) sets (11) all the tags in the floatingpoint unit, so the floating-point registers are listed as empty. Must be executed before the return instruction at the end of any MMX procedure.
or a subsequent floating-point operation will cause a floating-point interrupt error, crashing Windows or any other application

All other MMX instructions clear the tags, indicating all floating-point registers are in use.

Instruction Listing
Table 1 lists all MMX instructions with the machine code so they can be used with the assembler. MASM does not support these instructions unless you have the latest version (6.15). Any MMX instruction can be used inside Visual C++ using the inline assembler.