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Wasted Resources
Wasted resource wr(vi) of a node vi: Unused area occupied by the node vi during the computation of a partition.
wr(vi) = (t(Pi)ti)ai, t(Pi): run-time of partition Pi. ti: run-time of the component vi ai: area of vi
Wasted resource avoidance: A component is placed on the chip only when its computation is required and remains on the device only for time it is active.
Idle components can be replaced by new ones.
Temporal Placement
Temporal placement: Time-dependent placement Management of task execution at run-time Graphical Representation: Z axis: life time of a configuration. Some overlaps (resource sharing) in 2-D is allowed:
If not at the same time.
A horizontal cut:
Temporal Placement
Off-line (compile time)
Pre-defined placement sequence In DSP applications, program flow can be predicted.
[Bazargan]
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1. Place it in the first free location. Advantages: Fast (linear w.r.t. number of free locations) Disadvantages: Unused resources very high Fragmentation
CLBs
Frames
Fragmentation Simplifying the problem: Restricting the modules to columns (Virtex II) or part of a column (Virtex 4 / Virtex 5 / Virtex 6).
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ILP
ILP: Can construct a constraint set An objective function Advantage: Exact solution Limitation: Only for small size problems.
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Packing Approach
1. Variations of Packing Problem: Base Minimization Problem (BMP): Given a set of boxes B and a height H, find a container with minimal size (x, y, H) that can accommodate the set of boxes B i.e. in temporal placement:
Find the device with minimum size (x, y) on which a set of components can be implemented given an overall run-time t = H.
1.
Strip Packing Problem (SPP): Given a set of boxes and a base (X, Y), find the minimum height h container with size (X, Y, h) that can hold all the boxes. i.e. in temporal
Find the minimum run-time t = h for a set of components given a reconfigurable device with size (X, Y).
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KAMER
Assumption: No communications among RFUs After running an operation on RFU, results are saved in CPU registers
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Example
Non-ER: (E,F) ER: (E,D): MER (A,D): MER (E,C): not MER KAMER method: keeping all maximum empty rectangles:
Permanently keeps track of all MERs Whenever a request for placing a component v arrives, the list of MERs is searched for a rectangle that can accommodate v.
Possible to have many MERs in which v can fit Strategies: first-fit or best-fit
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KAMER
Once a rectangle is chosen:
Candidate points are those that do not allow an overlap with the external part of the rectangle.
Problem: Number of empty rectangles does not grow linear with the number of components included
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KAMER
Run-time of free rectangle placement: O(n2) Heuristic: Keep only the non-overlapping empty rectangles
Linear time, lower quality
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Can fit
Cant fit
(bad decomposition)
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Cant fit
Can fit
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Cant fit
Vertical Solution: Delaying the split decision for a number of steps later
Can fit
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If communication exists: An optimal algorithm should consider any single point Solution: [Ahmadinia04]
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Packing Classes
Interval Graph: Given a DFG G = (V,E), a reconfigurable device H and a packing of V into H, (i.e. a 3-D placement of the components of V on the device H), an interval graph of G is a graph Gi = (V,Ei), i {1, 2, 3} such that: (vk, vl) Ei the projections of the nodes vk and vl overlap in the i-th dimension. Complement Graph: Complement of interval graph: Gi = (V,Ei)
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Packing Class
Gi is i-feasible i {1,2,3} (wi(S) = vS wi(v) hi) (each set of boxes must fit in the container in the i-th direction)
Independent Set S: v,w S, v overlaps with w in dimension (3-i),
i{1,2}
C2: i=1...d Ei =
. There must be at least one dimension in which the boxes do not overlap.
Packing Class
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Packing Class
Invalid two-dimensional packing:
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Packing Class
Theorem: A d-tuple of graphs Gi(Vi,Ei) corresponds to a feasible packing, if and only if it is a packing class. Comparability Graph: Given a DFG G = (V,E), a reconfigurable device H and a packing of V into H, The comparability graph of an interval graph Gi = (V,Ei), i {1, 2} is the directed graph Gi = (V,Ei), where (vk, vl) Ei vl is placed after vk in 3-rd dimension, i.e. (pt(vk) + tk pt(vl)).
The relation place after defined by the comparability graph is a transitive relation also known as transitive orientation that can be used for orienting the packing classes.
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Algorithm
Can check if a given arrangement of nodes forms a valid packing with some precedence constraints fulfilled. Build arrangements on which we can apply the formulas to check whether the arrangement is a solution. If we have a set of available solutions, we need to extract the optimal one. Arrangements can be constructed by arbitrarily fixing/changing the edges of the different graphs as well as their orientations.
solution space: The set of all possible arrangements that can be built. Can be extremely large.
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Algorithm
Incremental approach: Constructs a tree from the root to the leaf: Root consists of the set of available nodes. Inserts edges to the already existing graph Two different insertions of edges on the same node two different branches in the tree. In each step: A new edge is included into the graphs, The validity of the resulting placement is checked. If the resulting placement not valid,
then all possible arrangement in which the introduced edges exist are discarded from the search. Otherwise, a new edge is added to the constructed graph.
Whenever a branch does not lead to valid leaf, the complete subtree resulting from the introduction of a new branch is discarded.
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References
[Bobda07] C. Bobda, Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications, Springer, 2007. [Hauck08] S. Hauck, A. DeHon, "Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation" MorganKaufmann, 2007 [Mehdipour06] F. Mehdipour*, M. Saheb Zamani, M. Sedighi, An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems, Journal of Microprocessors and Microsystems, Elsevier, v30, 2006, pp. 5262. [Bazargan00] K. Bazargan, R. Kastner and M. Sarrafzadeh, "Fast Template Placement for Reconfigurable Computing Systems," IEEE Design and Test - Special Issue on Reconfigurable Computing, January-March 2000. [Bazargan] Bazargan, Fast Placement Methods for Reconfigurable Computing Systems, http://www.ece.umn.edu/~kia/Research/Pre2000/RCSPlace/ [Ahmadinia04] A. Ahmadinia, C. Bobda, M. Bednara, and J. Teich, A new approach for on-line placement on reconfigurable devices, in Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS) / Reconfigurable Architectures Workshop (RAW), 2004.
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