Review of MOST

L
W
t
ox
Threshold voltage





( )
ox
Si A
F SB F T T
C
qN
V V V
c

| |
2
2 2
0
=
+ + =
Body
effect
coefficient
Body effect
V
T0
V
SB
(V)
MOS transistor characteristics
Linear I-V Equation for V
DS
< V
GS
- V
T


( ) | |
2
2
1
DS DS T GS ox n D
V V V V
L
W
C I =
Saturation I-V Equation for V
DS
> V
GS
- V
T

I
D
=
n
C
ox
(W/L) (V
GS
V
T
)
Channel Length Modulation
As V
DS
is increased, pinch-off point moves closer to
source - Effective channel length becomes shorter -
Current increases due to shorter channel
Summary: MOS I-V
Drain voltage V
DS

D
r
a
i
n

c
u
r
r
e
n
t

I
D
S

V
GS1

V
GS2

V
GS3

Linear
Saturation
without
channel-length
modulation
with
channel-
length
modulation
V
DS
= V
GS
-V
T
MOS Energy Band Diagram
qu
M

E
C

E
i

E
Fp

E
V

qu
Si

E
C,oxide

E
Fm

oxide
bandgap
8ev
Metal
p-type Si
E
Fp
E
V
E
C
Bands must bend for Fermi levels to line up - Part of
voltage drop occurs across oxide, rest occurs next to O-S
interface - Amount of bending is equal to work function
difference: qu
M
- qu
Si

E
i
E
Fm
q|
F q|
S
|
F
= Fermi
potential in bulk
|
S
= surface
potential
Definition of Inversion
Surface potential is same as |
F
, but of different sign
E
V
E
Fp
E
i
E
C
q|
F
q|
S
= -q|
F
ox
ox
ox
B
F FB T
C
Q
C
Q
V V =
0
0
2|
V
FB
= u
m
- u
Si

F Si A B
qN Q | c 2 2
0
=
Q
ox
= qN
ox

MOS capacitances
Oxide Capacitance
Gate to Source overlap
Gate to Drain overlap
Gate to Channel/Bulk
Junction Capacitance
Source to Bulk junction
Drain to Bulk junction
Oxide capacitances - overlap

Gate electrode overlaps source and drain
L
D
is overlap length on each side
source drain
L
D
D ox GDO GSO
WL C C C = =
Oxide capacitances gate voltage & channel charge

Gate-to-source: C
gs
Gate-to-drain: C
gd
Gate-to-bulk: C
gb

At Cutoff - No channel links surface to source and drain.
Hence, C
gs
= C
gd
= 0,
C
gb
is approximated as C
gb
= C
ox
WL

source drain
C
gb
C
gd
C
gs
Linear mode - Channel spans from S to D - Capacitance
split approximately equally between S and D
WL C C
ox GS
2
1
=
WL C C
ox GD
2
1
=
0 =
GB
C
Inversion layer shields substrate from gate field.
Saturation mode - Channel is pinched off:
0 =
GD
C
0 =
GB
C
WL C C
ox GS
3
2
~
Oxide capacitances
V
GS
Junction Capacitance
P-N Junction Capacitance
Zero-bias cap/area =
a d
a d Si
j
N N
N N
V
q
C
+
=
0
0
2
c
m
j
j
V
V
AC
C
|
|
.
|

\
|

=
0
0
1
General form:
V
o
is the built-in junction potential
m is the grading coefficient
= for abrupt junction, = 1/3 for linearly graded junction
(A is the junction area)
Junction Capacitance
Junction with substrate
Bottom area = W * L
S
(length of drain/source)
Side facing channel: area = W * X
j
Total cap = C
j

Junction Capacitance
Junction with sidewalls
Channel-stop implant - p
+
Perimeter = 2L
S
+ W
Area = P * X
j _
Total cap = C
jsw

Total junction cap C = C
j
+ C
jsw
Linearizing the Junction Capacitance
Replace non-linear capacitance by a large-signal
equivalent linear capacitance which displaces equal
charge over voltage swing of interest
Reverse bias across the junction is assumed to change
from V
1
to V
2

The equivalent linear cap is obtained by integrating
C
j
(V) between V
1
and V
2,
where C
j
(V) is given by:

m
j
j
V
V
AC
C
|
|
.
|

\
|

=
0
0
1
( )( )
0
1
0
1
1
0
2
1 2
0 0
1 1
1
j eq
m m
j
eq
C AK
V
V
V
V
m V V
V AC
C =
|
|
.
|

\
|
|
|
.
|

\
|

|
|
.
|

\
|

=

( )
( )
1 0 2 0
1 2
0
2
V V V V
V V
V
K
eq

=
(for m = )
0 0
) (
jsw eqsw j j eq j db
C K PX C K WX WL C s + + =
0 < K
eq
< 1
( )( )
0
1
0
1
1
0
2
1 2
0 0
1 1
1
j eq
m m
j
eq
C AK
V
V
V
V
m V V
V AC
C =
|
|
.
|

\
|
|
|
.
|

\
|

|
|
.
|

\
|

=

Electrostatic Discharge (ESD)
The thin and, therefore, very vulnerable gate oxide of the
MOST makes protection against destruction as a result
of electrostatic discharges, essential. The protective
precaution that was taken initially, and which is still the
best method, is the integration of clamping diodes, which
limit the dangerous voltages and conduct excess currents
into regions of the circuit that are safe. The safe regions
consist primarily of the supply-voltage connections.
ESD-Protection Circuits
In the simplest case, the protection circuits consist of
diodes that are oriented to be blocking in normal
operation, and are situated between the connection to the
component to be protected and the supply voltage lines
The diode approach can be made to work better by a
series resistor added in front of the diodes to limit the
magnitude of the ESD current and a bulk capacitance
added across the power supply rails.
To tolerate even higher energy levels, and to protect the
more sensitive parts of a circuit, two-stage protection
circuits frequently are used at the inputs. With this
arrangement, the coarse protection conducts away the
higher energy levels.
Diode D1 protects against negative voltages .
Positive voltages are first limited by transistor Q1, which begins to
conduct as soon as the input voltage (V
in
> Vdd + 0.7 V) allows
current to flow through resistor R1. If the input voltage increases
further, at about 22 V to 26 V, the thick-oxide MOS field-effect
transistor Q2 conducts. Q2 provides additional base current to the
base of transistor Q1. In this way, the energy in the interfering
pulse is conducted away reliably.
The fine protection circuitry, which should protect the next device
(primarily the gate oxide of the transistors) from excessive
voltages, consists of resistor R2 and Zener diode D2/D3.
Power supply noise
Voltage drops across parasitics cause variation in the
voltage of a single supply ( VDD or GND) from one point
in the system
If signal is referenced to local supply, this variation
results in additive voltage noise
Latch-up
Isolation of the individual diodes, transistors, and capacitors
from each other in an IC is achieved by reverse-biased P-N
junctions.
During the development of the circuit, precautions are taken
to ensure that these junctions always are reliably blocking
under the conditions that can be expected in the application.
However, these P-N junctions form N-P-N and P-N-P
structures with other adjacent junctions.
The result of this is parasitic npn or pnp transistors, which
can be undesirably activated.
The current gain of these transistors is usually very
small ( < 1). As a result, considerable input current is
usually necessary to activate these transistors.
With sensitive analog circuits, interference and other
undesirable effects can occur.
Also, the transit frequency of these transistors is
comparatively low (f
T
~ 1 MHz), which means that very
short pulses are not able to turn on such transistors.
Here, the N-doped regions for source and drain of the N-channel
transistor and the cathodes of the clamping diodes have been
diffused into a P-doped substrate. The substrate is connected to the
most negative point in the circuit, usually the ground connection
(GND).
In normal operation, the N-doped regions have a voltage that
is more positive than the ground connection. In this way,
these P-N junctions are blocking.
The substrate now forms the base of a parasitic npn
transistor, while all N-doped regions that is, the drain and
source of the N-channel transistor and cathode of the
clamping diodes function as emitters.
The collector belonging to this transistor forms the well in
which the complementary P-channel transistor is located.
The latter, with its connections, forms a parasitic pnp
transistor.
The npn and pnp transistors form a
thyristor. The anode and cathode of
this thyristor are connected to the
supply voltage of the IC, while all
other points inputs and outputs
function as the gate of the thyristor.
As long as the voltages on the latter
connections stay more positive than
the ground connection and more
negative than V
CC
, correct operation
occurs. The base-emitter diodes are
blocking.
If there is a voltage at the input or output that is more positive
than the supply voltage, or more negative than the ground
connection , current flows into the gate of the thyristor.
If the amplitude and duration of the current are sufficient, the
thyristor is triggered.
With lines of several meters in length and overshoots of
correspondingly longer duration, the probability that the
thyristor might be triggered must be taken into account.
This applies at the interfaces with the outside world;
unacceptable over-voltages also often occur at this point.
An electrostatic discharge can trigger the parasitic
thyristor.
Even if the electrostatic discharges have a duration of
only a few tens of nanoseconds, when this happens, the
complete chip may be flooded with charge carriers,
which then flow away slowly, resulting in
the triggering of the thyristor.
Latch-up was a major problem in early CMOS
processes
Now, latch-up is mainly an issue for I/O circuits with
high current demands and possibly noisy voltages
Guard Rings in a CMOS Circuit
These guard rings form additional collectors for the parasitic
transistors. Such collectors are connected either to the positive or
negative supply-voltage connection of the IC
These additional collectors are placed considerably closer to
the base-emitter region of the transistor in question than the
corresponding connections of the complementary transistor.
As a result, the charge carriers injected into one of the two
transistors is diverted largely via these auxiliary collectors to
the positive or negative supply-voltage connection.
These precautions do not completely eliminate the
questionable thyristor.
However, the thyristors sensitivity is reduced to such an extent
that, under normal operating conditions, there should be little
risk of triggering the thyristor.