EMK310

Lecture 6 Introduction to PIC32

Prof. Tania Hanekom

References:
PIC32MX3XX/4XX Family Data Sheet PIC32 Family Reference Manual Programming 32-bit Microcontrollers in C

Device structure
PIC32MX architecture functional blocks: MCU Core System Memory System Integration Peripherals

Block diagram

MCU core : MIPS architecture

32-bit RISC MIPS32 M4K Core
MIPS (Microprocessor without Interlocked Pipeline Stages) RISC instruction set architecture developed by MIPS Computer Systems Pipelining
CPUs built up from number of dedicated sub-units, e.g. instruction decoders, ALUs (integer arithmetics and logic), load/store units (handling memory). Execution of instructions pass data from one to the next. Traditional non-optimized design: a particular instruction in a program sequence must be (almost) completed before the next can be issued for execution Pipelined architecture: successive instructions can overlap in execution, eg., at the same time a math instruction is fed into the
floating point unit, the load/store unit can fetch the next instruction.

MCU core : MIPS architecture (2)

Barrier to pipelining: some instructions (e.g. division) take longer to complete; CPU has to wait before passing next instruction into pipeline. One solution: series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream.
Interlocks: major performance barrier since they had to communicate to all the modules in the CPU which takes time

MIPS design: fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

MCU core : MIPS architecture (3)

Other difference between MIPS & RISC: handling of subroutine calls RISC: register windows
hardware implementation limits the maximum depth of multi-level calls Each subroutine call requires its own set of registers = required more real estate on the CPU + more complexity in design

MIPS: compiler find free registers for subroutines

facilitated by increasing the number of registers increases the performance of all tasks

MCU core: ALU & Load-store

Single Cycle ALU Load-Store Execution Unit
Load-store = values in memory must be brought into the register file before they can be operated upon

MCU core: Pipeline

5-Stage Pipeline
Instruction (I ) Stage
instruction is fetched

Execution (E) Stage

Operands are fetched ALU begins arithmetic or logical operation

Memory (M) Stage

ALU operation completes data SRAM access performed

Align (A) Stage

separate aligner aligns loaded data with its word boundary

Writeback (W) Stage

result is written back to the register file

MCU core: Buses & GPRs

32-bit Address and 32-bit Data Buses Two 32-element, 32-bit General Purpose Register Files
copy of the General Purpose Registers (GPR) for use by high-priority interrupts = shadow register set shadow set minimize context switching overhead during interrupt/exception processing used for integer operations and address calculation

MCU core: FMT

FMT Fixed Mapping Translation Memory Management
FMT allows PIC32 to conform to programming model used by all other MIPS-based designs so that standardized address spaces are used. MIPS core: advanced features to allow separation of memory space dedicated to application(s) from that of operating system via use of memory management unit (MMU) and two distinct modes of operation: user and kernel. MMU replaced by simpler fixed mapping translation (FMT) unit and a bus matrix (BMX) control mechanism because embedded applications are less complex. compatible scheme simplifies design of tools, applications and porting of code to PIC32

MCU core: FMDU

FMDU Fast-Multiply-Divide Unit
PIC32 contains separate pipeline for multiply and divide operations. Pipeline operates in parallel with integer unit (IU) pipeline supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Divide operations implemented with 1 bit per clock iterative algorithm.

MCU core: Instruction set

MIPS32 Compatible Instruction Set MIPS16e Code Compression Instruction Set Architecture Support

System Memory
The PIC32 core offers some pretty advanced features never before seen on 8- or 16-bit PIC architectures. These include the ability to remap memory spaces, to cache memory contents, and to share the memory bus with a direct memory access (DMA) mechanism.

System memory: Virtual memory

PIC32MX microcontrollers implement two address spaces: virtual and physical.
All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions. (MIPS compatible) Physical addresses are used by peripherals, such as DMA and Flash controllers, that access memory independently of the CPU.

4 GB unified virtual memory address space

All memory regions, including program memory, data memory, SFRs and configuration registers reside in this address space at their respective unique addresses. Program and data memories can be optionally partitioned into user and kernel memories. Data memory can be made executable, allowing the PIC32MX to execute from data memory.

Virtual memory vs Physical memory

Flash Memory Technology

System memory provides on-chip nonvolatile Flash memory and volatile SRAM memory Flash
can be used for program memory or data. allows program memory to be electrically erased or programmed under software control during normal device operation. has the capability to page erase, word or row program.

The PIC32MX series has full-speed execution directly from program Flash through the use of on-chip prefetch buffering by the Prefetch module.

System Integration
System integration consists of a comprehensive set of modules and features that tie the MCU core and peripheral modules into a single operational unit. System integration features also provide these advantages:
Decreased system cost, by bringing traditionally off-chip functions into the microcontroller Increased design flexibility, by adding a wider range of operating modes Increased system reliability, by enhancing the ability to recover from unexpected events

System integration (continued)

The following sections of the PIC32 Family Reference Manual discuss the PIC32MX system integration:
Section 3. Memory Organization Section 4. Prefetch Module Section 5. Flash Programming Section 6. Oscillator Section 7. Resets Section 8. Interrupts Section 9. Watchdog Timer and Power-up Timer Section 10. Power-Saving Modes Section 31. Direct Memory Access (DMA) Controller with programmable Cyclic Redundancy Check (CRC) Section 32. High-Level Integration (Configuration, Code Protection and Voltage Regulation) Section 33. Device Programming, Debugging, In-Circuit and In-Circuit Testing

Peripherals
P32RM Section 12. I/O Ports P32RM Section 13. Parallel Master Port P32RM Section 14. Timers P32RM Section 15. Input Capture Module P32RM Section 16. Output Compare/Pulse Width Modulation (PWM) Module P32RM Section 17. 10-bit A/D Converter P32RM Section 19. Comparator Module P32RM Section 20. Comparator Voltage Reference Module P32RM Section 21. UART Module P32RM Section 23. SPI Module P32RM Section 24. I2C Module P32RM Section 27. USB OTG P32RM Section 29. Real-Time Clock/Calendar (RTCC) Module

Device structure (recap)

PIC32MX architecture functional blocks: MCU Core System Memory System Integration Peripherals

Block diagram revisited

Coding lecture
Intro to MPLAB C32 Flashing an LED