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Topics Covered
1.Introduction 2.Multifunction Implementation 3.The General Architecture Of Reconfigurable Processor 4.Architecture 5.Reconfigurable Processing Fabric 6.Programmable I/O 7.Technologies Used In Chip 8.Design Process 9.Comparison With Other Technologies 10.Advantages 11.Disadvantages 12.Applications 13.References 14.Conclusion
1.Introduction
A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself Dynamically. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. Reconfigurable processor chip usually contains several parallel processing computational units known as functional blocks. While reconfiguring the chip, the connections inside the functional blocks and the connections in between the functional blocks are changing, that means when a particular software is loaded the present hardware design is erased and a new hardware design is generated by making a particular number of connections active while making others idle.
This will define the optimum hardware configuration for that particular software. It takes just 20 microseconds to reconfigure the entire processing array. Reconfigurable processors are currently available from Chameleon Systems, Billions of Operations (BOPS), and PACT (Parallel Array Computing Technology). Among those only Chameleon is providing a design environment, which allows customers to convert their algorithms to hardware configuration by themselves.
2.Multifunction Implementation
In a conventional ASIC or FPGA, multiple algorithms are implemented as separate hardware modules. Four algorithms would divide the chip into four functional areas. With Reconfigurable Technology, the four algorithms are loaded into the entire reconfigurable Fabric one at a time. First, the entire Fabric is dedicated to algorithm 1; during this processing time, algorithm 2 is loaded into the background place. In a single clock cycle, the entire Fabric is swapped to algorithm 2; during this processing time, algorithm 3 is loaded into the background plane. The entire reconfigurable fabric is dedicated to just one algorithm at a time. So finally the result is: much higher performance, lower cost and lower power consumption
4.Architecture
Components:
32-bit Risc ARC processor @125MHz 64 bit memory controller 32 bit PCI controller reconfigurable processing fabric (RPF) high speed system bus programmable I/O (160 pins) DMA Subsystem Configuration Subsystem
The high-performance 32bit Data path Unit (DPU): The Tile includes seven Data path Units. The DPU is a data processing module that directly supports all C and Verilog operations.
6.Programmable I/O
RCP includes banks of Programmable I/O (PIO) pins which provide tremendous bandwidth. Each PIO bank of 40 PIO pins delivers 0.5 GBytes/sec I/O bandwidth.
3. eBIOS:
It provides a interface between the Embedded Processor System and the Fabric. eBIOS provides resource allocation, configuration management and DMA services. The eBIOS calls are automatically generated at compile time, but can be edited for precise control of any function.
8.Design Process
The reconfigurable processor, an entirely new category of semiconductor solution that serves as a system-level platform for a broad range of applications.
10.Advantages
can create customized communications signal processors
11.Disadvantages
Inertia Engineers slow to change Inertia is the worst problem facing reconfigurable computing RCP designs requires comprehensive set of tools 'Learning curve' for designers unfamiliar with reconfigurable logic
12.Applications
Wireless Base stations- The reconfigurable technology mainly focuses on base stations and their unpredictable combination of voice and data traffic.Base-station infrastructure will have to be adaptive enough to accommodate those requirements. With a fixed processor the channels must be able to support both simple voice calls and high-bandwidth data connections Wireless Local Loop (WLL)- Reconfigurable technology is widely applied in Wireless Local Loops also because of their high processing power, bandwidth and reconfigurable nature. High-Performance DSL (Digital Subscriber Line Technology)- DSL technology brings high Bandwidth to homely users. Software-Defined Radio (SDR)- SDR concept is applied in Cell phone Technology
13.Conclusion
These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the outmost speed. Its applications are in, data-intensive Internet,DSP,wireless basestations, voice compression, software-defined radio, high-performance embedded telecom and datacom applications, xDSL concentrators,fixed wireless local loop, multichannel voice compression, multiprotocol packet and cell processing protocols. Its advantages are that it can create customized communications signal processors ,it has increased performance and channel count, and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk.
References
Wei Qin Presentation , Oct 2000 (The part of the presentation regarding