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To reduce wastage of space on the substrate. To improve interconnections among different wafers.
To reduce the length of interconnections which in turn reduces heat dissipation and also RC delays.
Can be used to accommodate both homogenous and heterogeneous chips. Thus there is a great urge to switch over from 2D ICs to 3D ICs
The substrate is divided into blocks The similar characterized active components are stacked in the same block. This results in ease of interconnection.
GLOBAL TIERS Inter communicating blocks used for clock and power supply
BEAM RECRYSTALLISATION:
It offers flexibility for fabricating multiple layers, used mostly for stacking SRAM and EPROM.
Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
Wire length reduction has an impact on the cycle time and the energy dissipation Energy dissipation decreases with the number of layers used in the design
Natural to think of a 3D integrated circuit as being partitioned into device layers or planes Min cut partitioning along the 3rd dimension is same as minimizing vias
Routing in 3D consists of routing a set of aligned congruent routing regions on adjacent wafers.
Wires can enter from any of the sides of the routing region in addition to its top and bottom 3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias
LOOSE ROUTING
DETAILED ROUTING
MAGIC is an open source layout editor developed at UC Berkeley It is an extension to MAGIC by providing support for Multi-layer IC design.