Você está na página 1de 388

SISTEM MIKROPEMPROSES & PENGAWALMIKRO

(E 4160)
Thava kumar A/L Devanayagam 1

Chapter 1
Pengenalan kepada mikropemproses Introduction to Microprocessors

Thava kumar A/L Devanayagam

What is a Microprocessor ?
A microprocessor is a multipurpose, clockdriven, register-based electronic device that reads binary instructions from a storage device called memory, accept binary data as input and processes data according to the instructions given and provides results as output. Ex: 8085, 8086, Z80, 6800, Pentium processors etc

Thava kumar A/L Devanayagam

Microprocessors
The microprocessor is a programmable integrated device that has computing and decision-making capability similar to that of the central processing unit (CPU) of a computer. The fact that the microprocessor is programmable means it can be instructed to perform given tasks within its capability. The microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique.
Thava kumar A/L Devanayagam 4

Microprocessors
A typical MPU has three basic parts inside. They are:
the Program Counter (PC) Memory, and Input / Output (I/O).

The Program Counter keeps track of which command is to be executed. The Memory contains the commands to be executed. The Input / Output handles the transfer of data to and from the outside world (outside the MPU physical package). There are many other actual parts inside the MPU, however, we will learn about every single one, one step at a time.
Thava kumar A/L Devanayagam 5

Microprocessors
Nowadays, the microprocessor is being used in a wide range of products called microprocessor-based products or systems. The microprocessor can he embedded in a larger system, can be a stand alone unit controlling processes, or it can function as the CPU of a computer called a microcomputer.
Thava kumar A/L Devanayagam 6

Microprocessors
The microprocessor communicates and operates in the binary numbers 0 and 1, called bits. Each microprocessor has a fixed set of instructions in the form of binary patterns called a machine language. It is difficult for humans to communicate in the language of 0s and 1s. Therefore, the binary instructions are given abbreviated names, called mnenomics, which form the assembly language for a given microprocessor.
Thava kumar A/L Devanayagam 7

Microprocessors
A typical programmable machine can be represented with four components: microprocessor, memory, input, and output. These four components work together or interact with each other to perform a given task; thus, they comprise a system. The physical components of this system are called hardware. A set of instructions written for the microprocessor to perform a task is called a program, and a group of programs is called software.
Thava kumar A/L Devanayagam 8

Microprocessors
The microprocessor applications are classified primarily in two categories:
reprogrammable systems and embedded systems.

Thava kumar A/L Devanayagam

Microprocessors
In reprogrammable systems, such as microcomputers, the microprocessor is used for computing and data processing. These systems include:
general-purpose microprocessors capable of handling large data, mass storage devices (such as disks and CD-ROMs), and peripherals such as printers; a personal computer (PC) is a typical illustration.
Thava kumar A/L Devanayagam 10

Microprocessors
In embedded systems, the microprocessor is a part of a final product and is not available for reprogramming to the end user. Example:
copying machine washing machine. Air-conditioner Etc.
Thava kumar A/L Devanayagam 11

Microprocessor, CPU & Microcontroller


Microprocessor (MPU) - a semiconductor device (integrated circuit) manufactured by using the LSI technique.
It includes the ALU, register arrays, and control circuits on a single chip.

CPU - the central processing unit.


The group of circuits that processes data and provides control signals and timing. It includes the arithmetic/logic unit, registers, instruction decoder, and the control unit.

Microcontroller - a device that includes microprocessor, memory, and I/O signal lines on a single chip, fabricated using VLSI technology.
Thava kumar A/L Devanayagam 12

Microprocessor, CPU & Microcontroller


In large computers, a CPU implemented on one or more circuit boards performs these computing functions. The microprocessor is in many ways similar to the CPU, but includes all the logic circuitry, including the control unit, on one chip.
Thava kumar A/L Devanayagam 13

Traditional block diagram of a computer


Thava kumar A/L Devanayagam 14

Block diagram of a computer with the microprocessor as a CPU


Thava kumar A/L Devanayagam 15

Block diagram of a microcontroller


Thava kumar A/L Devanayagam 16

Basic Concepts of Microprocessors


Differences between: Microcomputer a computer with a microprocessor as its CPU. Includes memory, I/O etc. Microprocessor silicon chip which includes ALU, register circuits & control circuits Microcontroller silicon chip which includes microprocessor, memory & I/O in a single package.
Thava kumar A/L Devanayagam 17

Arithmetic Logic Unit (ALU) This is the area of microprocessor where various computing functions are performed on data. Control Unit The control unit provides necessary timing and control signals to all operating units in the microcomputer. It controls the flow of data between microprocessor, memory and peripherals. Memory Memory unit stores group of binary digits (word) that can represent: a. instructions (program) that the computer is to perform. b. the data that are to be operated on by the program. Input Consists of all of the devices used to take information and data from the external environment to be inputted into the computer system. Output (I/O) Consists of all of the devices used to transfer information and data from computer system to the external environment.
Thava kumar A/L Devanayagam 18

Definisi Mikrokomputer : Ahli terbaru keluarga komputer, yang mengandungi cip mikropemproses, cip ingatan dan antara mukaan I/O. Dalam beberapa kes, semua yang disebut berada dalam satu cip tunggal

Thava kumar A/L Devanayagam

19

UNIT CPU (CENTRAL PROCESSING UNIT) UNIT MEMORI

Satu cip silikon yang bekerja sebagai heart komputer. Menerima arahan daripada memori utk mengimplementasikan tugas.

Menyimpan data dan program. Terbahagi kepada 2 kategori:

Thava kumar A/L Devanayagam

20

1. MEMORI UTAMA:

1.

RAM (Random Access Memory): Data boleh dibaca dan disimpan. Data yang disimpan akan hilang apabila bekalan diputuskan. ROM (Read Only Memory): Data boleh dibaca tetapi tidak bolehditulis. Data yang disimpan tidak akan hilang apabila bekalan diputuskan.

2.

2. MEMORI KEDUA:

RAM boleh menyimpan data sementara. Contohnya floppy disc,,harddisk dan CDROM (Compact-disc ROM), yang mana boleh menyimpan kepada 600 million characters dan sesuai untuk menyimpan maklumat yang bersaiz besar.
Thava kumar A/L Devanayagam 21

UNIT INPUT/OUTPUT (I/O):

Mengandungi litar antaramuka yang diperlukan untuk membenarkan persisian dihubungkan komponen lain. Contoh litar antaramuka ialah cip-cip LSI direka oleh pengeluar MPU untuk mengantaramuka MPU ke pelbagai komponen input/output. Contoh litar antaramuka yang mudah ialah daftar buffer. Unit I/O membenarkan pengguna untuk berkomunikasi dengan sistem komputer melalui antaramuka untuk berkomunikasi dengan komponen persisian. Contoh persisian ialah keyboard, printer dan sensor Saiz port input/output ialah sama dengan saiz bas data mikropemproses.
22

Thava kumar A/L Devanayagam

TAHUN 1971

SYARIKAT Intel

INOVASI 4004 - mP 4 bit pertama: ingatan 1K

1972
1974

Intel
Intel Motorola

8008 - mP 8 bit pertama: ingatan 16K


8080 - mP 8 bit serbaguna pertama: ingatan 64K 6800 - mP 8 bit pertama drp motorola 6502 - mP 8 bit yg diguna dlm Apple/ mkomputer pertama Z80 - mP 8 bit serasi 8080

1975

MOS Zilog

1976
1978 1980 1982

Intel
Intel Intel Intel Motorola

8086 - mP 16 bit ; ingatan 1M


8086 mP 16/32 bit ; diguna dlm Apple Macintosh 8088 8086 dgn bas data bit ; diguna dlm IBM PC 80286 - 8086 dgn ingatan maya ; ingatan 16M 68008 68000 dgn bas 8 bit ; ingatan 16M 68010 - 68000 dgn ingatan maya

1983

Motorola

1984
1985 1987 1989

Motorola
Intel Motorola Intel

68020 - mP 32 bit ; ingatan 4G


80386 mP 32 bit 68030 68020 dgn unit pengurusan ingatan (MMU) 80486 80386 yg lebih laju; unit titik-apung (FPU) bina dlm Thava kumar A/L Devanayagam 23

TAHUN

SYARIKAT Motorola

INOVASI 68040 68030 yg lebih laju (FPU) bina dlm Pentium - 80486 yg lebih laju; superskalar; FPU + 2 ALU

1993

Intel

Motorola/IBM/ Power PC mP RISC Apple 1994 2003 Motorola AMD Intel 68060 68040 yg lebih laju; superskalar; FPU + 2 ALU the first 64-bit IA-32 backwards-compatible architecture, AMD64 x86-64 chips, the 64-bit desktop Both processors can run 32-bit legacy apps as well as the new 64-bit software. With 64-bit Windows XP, Linux and Mac OS X (to a certain extent) that run 64-bit native dual-core processors are widely used in high-end servers and workstations while quad-core processors for servers are beginning to become available.

2006

Intel

Thava kumar A/L Devanayagam

24

DATA SIZE (N) 1 4 8

DATA TYPES

DATA CAPASITY 2N

RANGE 01 0 - 15 0 255

Bit Nibble Byte

2 16 256

16
32

Word
Long Word

65536
4,294,967,296

0 65535
0 - 4,294,967,295
25

Thava kumar A/L Devanayagam

FETCH AND EXECUTE CYCLES


START

Fetch (next) Instruction 3) Microprocessor continue the next instruction. Execute Instruction

1: Microprocessor fetch instruction representing the signal carried by the address bus.

2: Microprocessor execute the instruction.

NO

Is it a HALT instruction?
YES

END
Thava kumar A/L Devanayagam 26

KITAR AMBIL (FETCH CYCLE)


uP Meletakkan alamat byte pertama suruhan pada bas alamat dgn isyarat kawalan, BACA dari lokasi ingatan yg dialamatkan (Contoh: alamat untuk byte pertama 0FF01H) Mengambil byte dari bas data. Byte ini dinamakan opkod. Dinyahkod dan isyarat yang perlu akan dijanakan.
Thava kumar A/L Devanayagam 27

uP Opkod

KITAR LAKSANA (EXECUTE CYCLE)


uP akan melaksanakan operasi yang diminta oleh suruhan.

Thava kumar A/L Devanayagam

28

Thava kumar A/L Devanayagam

29

The 8085 Hardware/Programming Model


A model is a conceptual representation of a real object. The microprocessor can be represented in terms of its hardware (physical electronic components) and a programming model (information needed to write programs).

Thava kumar A/L Devanayagam

30

8085 Hardware Model

Thava kumar A/L Devanayagam

31

8085 Hardware Model


Two major segments:
One segment includes the arithmetic/logic unit (ALU) and an 8-bit register called an accumulator, instruction decoder, and flags. The second segment shows 8-bit and 16-bit registers. Both segments are connected with various internal connections called an internal bus. The arithmetic and logical operations are performed in the ALU. Results are stored in the accumulator, and flip-flops, called flags, are set or reset to reflect the results
Thava kumar A/L Devanayagam 32

ALU

REGISTER SECTION

CONTROL UNIT AND TIMING SECTION


MICROPROCESSOR

Thava kumar A/L Devanayagam

33

Arithmetic Logic Unit (ALU) section:


Performs variety of arithmetic andlogic operations on data, such as addition, subtraction, AND, OR, EX-OR, shifting, incrementing, and decrementing. The more advanced MPU have ALUs that can do multiplication and divisions.

Thava kumar A/L Devanayagam

34

The 8085 Programmable Register

Thava kumar A/L Devanayagam

35

Registers section:
These internal registers serve as temporary data storage, before, in progress and after the process done by ALU. Data transfer within these registers is much faster as compared to the memory. This section contains various registers (inside the MPU), each of which performs a special function. These registers are: general purpose registers array, accumulator, instruction register, program counter, and flag register.
Thava kumar A/L Devanayagam 36

Accumulator
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A.

Thava kumar A/L Devanayagam

37

Flags
The following flags are set or reset after the execution of an arithmetic or logic operation; data copy instructions do not affect any flags. See the instruction set (Appendix F) to find how flags are affected by an instruction.
Z-Zero: The Zero flag is set to 1 when the result is zero; otherwise it is reset. CY - Carry: If an arithmetic operation results in a carry, the CY flag is set; otherwise it is reset. S - Sign: The Sign flag is set if bit D7 of the result = 1; otherwise it is reset. P - Parity: If the result has an even number of 1s, the flag is set; for an odd number of 1s, the flag is reset. AC - Auxiliary Carry: In an arithmetic operation, when a carry is generated by digit D3 and passed to digit D4, the AC flag is set. This flag is used internally for BCD (binary-coded decimal) operations; there is no Jump instruction associated with this flag.
Thava kumar A/L Devanayagam 38

Flag
Block Diagram
D7 D6 D5 D4 D3 D2 D1 D0

AC

CY

Thava kumar A/L Devanayagam

39

Example
Instruction:

ADD B
Register contents after instruction:
A B Flag
1001 1010 1000 1001 0010 0011

Register contents before instruction


A B Flag 9A h 89 h 80 h

23 h 89 h 10 h

Note: All flags are modified to reflect the result of the addition.
40

Flag: S=0, Z=0, AC=1 , P=0 and C=1,


Thava kumar A/L Devanayagam

1. Carry (CY)

i) C = 1, bendera carry disetkan oleh MSB setelah b8 b7 operasi dijalankan. 1 1 1


EE + 70 1 5E 1 1 1 0 +0 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 0

MSB: b7 b8 = 1 C=1

ii) C = 1 , Pinjam = 1 apabila terdapat pinjam pada 1011 0101 MSB


- 1100 1100 --------------Borrow 1 1110 1001

2. Zero (Z)

Z = 1, disetkan apabila keluaran adalah zero,


Operation MSB ....LSB 000000000000000000 Zero Z=1

Z = 0, disetkan apabila keluaran adalah tidak zero,


Operation MSB ....LSB 000100000000000000 MSB ....LSB 000001010001000000 Non-Zero Z=0

Operation

Non-Zero

Z=0

Thava kumar A/L Devanayagam

41

3. Sign (S)

S = 1, disetkan, apabila keluaran negatif.


Operation MSB ....LSB 1xxx..xxxx MSB =1 -ve S=1

S = 0, disetkan, apabila keluaran positif.


Operation MSB ....LSB 0xxx..xxxxx MSB =0 +ve S=0

Bendera S disetkan dgn melihat pada MSB keluaran.

4. Auxiliary Carry

Bendera ini akan disetkan apabila berlaku carry dari bit-3 ke bit-4 semasa operasi campur atau tolak. Bendera ini biasanya akan digunakan dalam operasi aritmetik BCD (binary Coded Decimal) Operasi: 2F16 00101111 + 3816 00111000 6716 01100111
Thava kumar A/L Devanayagam 42

5. Pariti (P)

Bendera pariti menunjukkan bilangan bit 1 yang ada dalam daftar penumpuk sahaja. Jika P =1 (ganjil) P = 0 (genap) Operasi: 9C16 10011100 4216 01000010 DE16 11011110 Bil. Bit adalah enam maka iaiti genap,P =0

Thava kumar A/L Devanayagam

43

General-purpose Registers
The 8085 has six general-purpose registers to store 8-hit data; B, C, D, E, H, and L. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions.

Thava kumar A/L Devanayagam

44

Program COUNTER (PC) AND STACK POINTER (SP)


These are two 16-bit registers used to hold memory addresses. PC:
The function of the PC is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location.

SP:
It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer. The PC will automatically update when calling to /returning from Subroutines.
Thava kumar A/L Devanayagam 45

16 Bit Registers
Program Counter
A pointer to the next instruction to be executed Contains the 16-bit memory address of the next instruction Updated after processor has fetched the instruction

6-bit register acting as memory pointer sequences the execution of instructions PC points to the memory address from which the next byte is to be fetched. while a byte being fetched it is incremented by 1 to point to next memory location.

Thava kumar A/L Devanayagam

46

Stack Pointer
Stack an area in memory in which temporary info is stored Stack FILO (First In Last Out) basis Holds the address of the top of the stack 16-bit register acting as memory pointer. SP points to the memory location in R/W memory (RAM), called the stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer (SP).
Thava kumar A/L Devanayagam 47

Control and timing section:


The main function is to fetch instruction codes from program memory. Then decode (interpret) them, to generate into necessary control signals from MPU Then to execute the instructions. This section also generates timing and control signals (eg. R/W clock), that are needed by external RAM, ROM, and I/O devices.
Thava kumar A/L Devanayagam 48

8085 Hardware Model


There are three buses:
a 16-bit unidirectional address bus to send out memory addresses; an 8-bit bidirectional data bus, and a control bus to transfer data, and. the control bus for timing signals.

Thava kumar A/L Devanayagam

49

Thava kumar A/L Devanayagam

50

Bus system
A wire is used to transfer a signal from one point to another. A group of wires is called bus. In the microcomputer system, there are three buses (data, address, and control) to connect the microprocessor (CPU) to each of the devices in the microcomputer system such as memory and I/O devices. These buses will carry (sending or receiving) all the information and signals involved in the system operation from one device to another.
Thava kumar A/L Devanayagam 51

DATA BUS
Bidirectional bus, because data can flow to or from the CPU. The size of data bus is determined by the number of lines (bits) which is also called data size. Data size: Size of single cell in the memory. Numbers of bit the CPU can handle at any one time. Intel 8085 microprocessorhas 8 bits data bus, thus: Data size n = 8 bits, Data lines are labelled Dn : D0, D1, .. D6, D7 In other words, the CPU can handle, or data bus can transfer 8 bits data in parallel simultaneously, thus determine the speed of data transfer. The same data bus (bits) can be set to either inputs or outputs depending on whether the CPU is performing a read or a write operation respectively.
Thava kumar A/L Devanayagam 52

ADDRESS BUS
Unidirectional bus, because information flows over it in only one direction, i.e. from CPU to the memory or I/O elements. The number of address lines (address bus size) determine the number of memory cells that CPU can handle. For instance, the Intel 8085 has 16 bits of address bus: n = 16 bits (Size of address bus): Address bus is labelled An : A0, A1, .. A14, A15 2n = 216 = 65536: CPU can handle or address 65536 single cells (each cell has 8 bits data size) of memory. In other words, 16 bit address lines can represent 65536 memory location: 0 to 65535 locations, addressed as 0000h to FFFFh

Thava kumar A/L Devanayagam

53

CONTROL BUS
This is the set of signals that is used to synchronize the activities of the separate microcomputer elements. Control bus consists some individual lines for sending and some others for receiving signals from CPU, thus control bus is bidirectional. For instance, CPU sends control signals (Read/Write) to the memory or I/O devices to tell them either to be set to receive or send data respectively. CPU send Control signal : Read Action: CPU receive data CPU send Control signal : Write Action: CPU send data
Thava kumar A/L Devanayagam 54

8085 Instruction Set


An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform.

Thava kumar A/L Devanayagam

55

Status Register (Daftar status/ Daftar bendera)

8 bit register shows the status of the


microprocessor before/after an operation S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) & CY (carry flag) storan bagi keputusan ujian-ujian tertentu terutama proses aritmetik dan logik Sign keputusan operasi logik/aritmetik menyebabkan msb bernilai 1 Zero keputusan bagi operasi logik/aritmetik adalah 0 Auxillary carry- apabila berlaku dari bit 3 ke bit 4. Parity- apabila bit 1 adalah genap.

Thava kumar A/L Devanayagam

56

Status Register

Carry carry dari bit ke bit 8

Thava kumar A/L Devanayagam

57

Kuiz 1

Jelaskan maksud istilah-istilah berikut :


Nibble Byte Word

Terangkan fungsi binaan dalam mikropemproses :


Unit Aritmetik dan Logik Accumulator Stack Pointer
Thava kumar A/L Devanayagam 58

executes each machine instruction by performing a fetch/execute cycle. CPU fetches an opcode byte from memory and decodes it to find out what it is supposed to do. CPU executes the instruction. instructions examine or modify memory or input and output (I/O). After the is completed, the cycle resumes instruction for the next instruction.
Thava kumar A/L Devanayagam 59

CPU

PERLAKSANAAN SURUHAN DALAM MIKROPEMPROSES


5 Bas Data 6 7 4

Daftar Arahan Penyahkod

Arahan dan data

Arahan
1 Pembilang Aturcara Mikropemproses
Thava kumar A/L Devanayagam

Penyahkod Alamat Ingatan


(Memory Address Decoder)

Bas Alamat 2 3

Ingatan
60

1 Alamat ingatan bagi suruhan pertama diletakkan ke pembilang aturcara 2 Pembilang aturacara akan meletakkan alamat ingatan tersebut ke bas alamat 3 Alamat ingatan kemudiannya dihantar ke ingatan 4 Ingatan menterjemahkan alamat tersebut dan kedudukan ingatan yang dikehendaki dapat dikesan 5 Ingatan akan menghantar suruhan kembali ke mikropemproses melalui talian bas data 6 Suruhan diletakkan di dalam Daftar Arahan dalam mikropemproses.
Thava kumar A/L Devanayagam 61

7 Mikropemproses menterjemah suruhan tersebut sebelum dilaksanakan 8 Pembilang aturcara akan ditokok dan mikropemproses bersedia menerima suruhan seterusnya

Thava kumar A/L Devanayagam

62

Chapter 2
PENGENALAN PENGAWAL MIKRO Introduction to Microcontroller

Thava kumar A/L Devanayagam

63

What is Microcontroller?
A microcontroller is an integrated chip that is often part of an embedded system. The microcontroller includes a CPU, RAM, ROM, I/O ports, and timers like a standard computer, but because they are designed to execute only a single specific task to control a single system, they are much smaller and simplified so that they can include all the functions required on a single chip. A microcontroller differs from a microprocessor, which is a general-purpose chip that is used to create a multifunction computer or device and requires multiple chips to handle various tasks. A microcontroller is meant to be more self-contained and independent, and functions as a tiny, dedicated computer.
Thava kumar A/L Devanayagam 64

DEFINITION
mC = single- chip microcomputer Contains on-chip resources typically used in embedded applications. May not requires extra off-chip resources to function. Ex: Intels 8051, 8096, Motorola M68HC11, PIC 16XX series etc.

Thava kumar A/L Devanayagam

65

mC APPLICATIONS
Applications Computing Example PC, Notebook, laser printer

Communications Wireless phone, cellular phone


Consumer Video games, camera

Cars
Cards

Engine control
Banking, Touch N Go
Thava kumar A/L Devanayagam 66

Ciri-ciri microcontroller
Rekabentuk bersifat All-in-one Ketegapan (Robustness) Keperluan Kuasa yang rendah (Low Power Consumption)

Thava kumar A/L Devanayagam

67

Microcontroller MCS-51 Architecture

Thava kumar A/L Devanayagam

68

The mC Unit (MCU)


Internally 3 Basic parts 1. Central Processing Unit (CPU) 2. Memory 3. Registers ( they are connected by an internal bus) 1. 2. 3. It has pins for power Input/output (I/O) Some special signals

Externally

Thava kumar A/L Devanayagam

69

The mC Unit (MCU)


CPU (Unit pemroses pusat) Controls the operation of the microcontroller i. ALU ii. Control iii. Register iv. Bus system

Thava kumar A/L Devanayagam

70

mC SYSTEM
Buffers & converter Bus Condition I/O signal levels if necessary Data,address and control Data = sinals represent instructions and values of different variables, such as temperature Address = indicate where data is stored Control = signals coordinate microcontroller operation with associated chips.

Thava kumar A/L Devanayagam

71

mC SYSTEM
Clock Circuit Generates a fixed-frequency signal that provides timing information for the entire system. a crystal connected to two pins of the microcontroller Power converts incoming power such as Circuit 115V alternating current (ac) or 12 V direct current (dc) to the nominal 5 V dc required to operate the microcontoller.
Thava kumar A/L Devanayagam 72

The mC Unit (MCU)


Memory Is where data and program code are stored. 3 types of memory: Read-only memory (ROM) Random-access memory (RAM) Electrically erasable programmable ROM (EEPROM) (some mCs use EPROM instead of ROM)

Thava kumar A/L Devanayagam

73

The mC Unit (MCU)


Registers are used to handle specialized information It is place where CPU works on (modifies) a binary number. There are I/O registers and CPU registers

Thava kumar A/L Devanayagam

74

Sistem Bas
Bas Alamat Kumpulan talian yang membawa isyarat alamat dari pemproses ke ingatan dan I/O supaya pemproses boleh mencapai lokasi dan port-port yang tertentu. Kumpulan talian yag membawa data dari pemproses ke ingatan dan port keluaran dari ingatan dan port masukan ke pemproses
75

Bas Data

Thava kumar A/L Devanayagam

Bas Kawalan

Kumpulan talian yang membawa isyarat kawalan untuk proses seperti baca dari RAM dan port, reset dan interrupt pemproses.

Thava kumar A/L Devanayagam

76

Microcontroller MCS-51 Architecture

Thava kumar A/L Devanayagam

77

Thava kumar A/L Devanayagam

78

Comparison of the 8051 Family Members

Feature 8051 ROM (program space in bytes) 4K RAM (bytes) 128 Timers 2 I/O pins 32 Serial port 1 Interrupt sources 6

8052 8K 256 3 32 1 8

8031 0K 128 2 32 1 6

Thava kumar A/L Devanayagam

79

Thava kumar A/L Devanayagam

80

Thava kumar A/L Devanayagam

81

Thava kumar A/L Devanayagam

82

Thava kumar A/L Devanayagam

83

Thava kumar A/L Devanayagam

84

Thava kumar A/L Devanayagam

85

Thava kumar A/L Devanayagam

86

Thava kumar A/L Devanayagam

87

Thava kumar A/L Devanayagam

88

Thava kumar A/L Devanayagam

89

Thava kumar A/L Devanayagam

90

Thava kumar A/L Devanayagam

91

Thava kumar A/L Devanayagam

92

Thava kumar A/L Devanayagam

93

Pin Description of the 8051


PDIP/Cerdip
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)
94

8051 (8031)

Pins of 80511/4
Vccpin 40 Vcc provides supply voltage to the chip. The voltage source is +5V. GNDpin 20ground XTAL1 and XTAL2pins 19,18 These 2 pins provide external clock. Way 1using a quartz crystal oscillator Way 2using a TTL oscillator Example 4-1 shows the relationship between XTAL and the machine cycle.
1

Thava kumar A/L Devanayagam

95

Pins of 80512/4
RSTpin 9reset It is an input pin and is active highnormally low. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers
Way 1Power-on reset circuit Way 2Power-on reset with debounce

Thava kumar A/L Devanayagam

96

Pins of 80513/4
/EApin 31external access There is no on-chip ROM in 8031 and 8032 . The /EA pin is connected to GND to indicate the code is stored externally. /PSEN ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSENpin 29program store enable This is an output pin and is connected to the OE pin of the ROM. See Chapter 14.
3

Thava kumar A/L Devanayagam

97

Pins of 80514/4
ALEpin 30address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.

Thava kumar A/L Devanayagam

98

XTAL Connection to 8051


Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND

Thava kumar A/L Devanayagam

99

XTAL Connection to an External Clock Source

N C Using a TTL oscillator XTAL2 is unconnected.


EXTERNAL OSCILLATOR SIGNAL

XTAL2

XTAL1

GND

Thava kumar A/L Devanayagam

100

Example :
Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 ms (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 ms

Thava kumar A/L Devanayagam

101

RESET Value of Some 8051 Registers:

Register PC ACC B PSW SP DPTR RAM are all zero.

Reset Value 0000 0000 0000 0000 0007 0000

Thava kumar A/L Devanayagam

102

Power-On RESET Circuit


Vcc

+ 10 uF 31 EA/VPP X1 X2

30 pF
8.2 K 30 pF

11.0592 MHz

19

18

9 RST

Thava kumar A/L Devanayagam

103

Power-On RESET with Debounce


Vcc

31 10 uF 30 pF

EA/VP X1 P X2 RST

9
8.2 K

Thava kumar A/L Devanayagam

104

Pins of I/O Port


The 8051 has four I/O ports Port 0 pins 32-39P0P0.0P0.7 Port 1pins 1-8 P1P1.0P1.7 Port 2pins 21-28P2P2.0P2.7 Port 3pins 10-17P3P3.0P3.7 Each port has 8 pins. Named P0.X X=0,1,...,7, P1.X, P2.X, P3.X ExP0.0 is the bit 0LSBof P0 ExP0.7 is the bit 7MSBof P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction).
Thava kumar A/L Devanayagam

105

Thava kumar A/L Devanayagam

106

Perbezaan Mikropemroses & Pengawal mikro


Mikropemproses IC tunggal tanpa RAM, ROM, atau I/O Pereka perlu menambahkan komponenkomponen(RAM,ROM dan IO) ini secara luaran untuk mikropemproses berfungsi Pengawalmikro terdiri CPU, RAM, ROM dan pengkalan I/O Pereka tidak boleh menambahkan ingatan luar atau pengkalan I/O

Thava kumar A/L Devanayagam

107

Pereka sistem boleh menentukan jumlah RAM, ROM dan pengkalan I/O yg diperlukan dalam sistem

Biasa digunakan untuk memproses data

Pereka sistem tidak boleh menentukan jumlah RAM, ROM dan pengkalan I/O kerana ia adalah tetap yg diperlukan dalam sistem Biasa digunakan untuk tujuan kawalan

Thava kumar A/L Devanayagam

108

Chapter 3
PENGENALAN KEPADA BAHASA PENGHIMPUN (SET SURUHAN) INTRODUCTION TO ASSEMBLY LANGUANGE

Thava kumar A/L Devanayagam

109

DEFINISI BAHASA
BAHASA ialah satu medium komunikasi di antara dua atau lebih individu atau kumpulan

Thava Kumar A/L Devanayagam

110

Language Categories
Three classes of Languages
High-level languages
Hide the detail of computer and O.S.

Platform-independent
C++,Java and Fortran

Assembly languages
Platform-specific Backward compatible
Thava Kumar A/L Devanayagam 111

Language Categories
Machine languages
Contain binary value Platform-specific

Thava Kumar A/L Devanayagam

112

PENGGUNAAN BAHASA DALAM SISTEM KOMUNIKASI


KOMUNIKASI ASAS
B A H A S A

SISTEM KOMUNIKASI KOMPUTER Pengaturcara Bahasa Tahap tinggi Bahasa Penghimpun Tahap Tinggi

JEPUN

P E N T E R J E M A H

Penterjemah

Compiler

Assembler

Tahap Pertengahan

B A H A S A

Bahasa mesin MELAYU

Bahasa mesin

Tahap Rendah

Komputer

Thava Kumar A/L Devanayagam

113

PERBEZAAN TIGA BAHASA


Manusia (Programmers)

COMPILERS (Pengkompil)

Bahasa Tahap Tinggi (Basic, Pascal and C) Arahan pengaturcaraan dalam english dan sangat mesra kepada pengguna programmers.. Bahasa Tahap Pertengahan (Bahasa penghimpun) Arahan pengaturcaraan dalam english seperti abbreviation masih tidak mesra kepada pengguna. ASSEMBLER (Penghimpun)

Bahasa Tahap Pertengahan (Bahasa Mesin))


Arahan pengaturcara dalam kod binari,difahami terus oleh sistem komputer

Sistem komputer mengimplementasi Thava Kumar A/L Devanayagam

114

Compiling and Assembling


Compiler convert the high-level language to machine code. And assembler convert the assembly language to machine code
To make sure every statement is valid.

To generate the object code.

Linker combines object code with any other required object code.
stored as in executable file.

Loader copies the execute file into memory.


Thava Kumar A/L Devanayagam 115

8085 Assembly Language Programming


Compiler: This is a program that translates English-like words, of a high-level language in the machine language of a computer. Interpreter: An interpreter is a program that translates the English-like statements of a high-level language into the machine language of a computer. Assembler: A computer program that translates an assembly language program from mnemonics to the binary machine code of a computer.

Thava Kumar A/L Devanayagam

116

PERBEZAAN KELEBIHAN

BAHASA PENGHIMPUN
Cepatkan penulisan bhs mesin, kod senang ingat atau singkatan kpd pkt mudah yg dikenali mnemonik mengantikan nilai perenambelasan

BAHASA TAHAP TINGGI


Arahan pengaturcaraan dalam english dan sangat mesra kepada pengguna Aturcara mudah ditulis dan mudah dialihkan ke sebarang mikropemproses lain jika perlu. Kod objek yg dihasilkan oleh pengkompil bhs thp tinggi selalunya beroperasi dgn lebih perlahan, saiz kod objek yang terhasil juga lebih besar drp kod objek oleh penghimpun. Maka, menggunakan ruang yang besar
117

KEKURANGAN

Arahan pengaturcaraan dalam english seperti abbreviation masih tidak mesra kepada pengguna.

Thava Kumar A/L Devanayagam

8085 Assembly Language Programming


Instruction Set: An entire group of instructions. Assembly Language Program: A set of instructions written in mnemonics of a given microprocessor such as 8085, 8086 etc. Mnemonic: A combination of letters to suggest the operation of an instructions (Mnemonic = mindful)

Machine Language: The binary medium communication with a computer through a designed set of instructions specific to each computer. Ex- 1000 0000 ADD B 80H Instructions in binary form machine lang. Mnemonic Hex codes This instruction adds the contents of register B to the accumulator.

Thava Kumar A/L Devanayagam

118

FF01

3E

MVI A,1

;load A with1

Alamat

Opcode

Mnemonik Operand

Komen

ALAMAT OPCODE MNEMONIK

Medan yang mewakili setiap baris aturcara bahasa penghimpun dgn lokasi alamat heksadesmal Medan yang mengandungi kod-kod operasi (heksadesimal) untuk set suruhan 8085 yang telah diterjemahkan dri mnemonik Mengandungi mnemonik suruhan bahasa penghimpun mnemonik suruhan diterjemahkan menjadi kod mesin yang boleh dilaksanakan pemproses pengaturcara memasukkan aturcara dgn lebih mudah, tanpa keperluan untuk menghafal nilai-nilai opkod Sesetengah suruhan memerlukan operand, terdapat suruhan tidak memerlukan operand Pengaturcara memasukkan penerangan ringkas mengenai setiap baris aturcara, setiap komen mestilah dimulakan dengan simbol (;)

OPERAND KOMEN

Thava Kumar A/L Devanayagam

119

Compilation process for high-level programs.

Thava Kumar A/L Devanayagam

120

Assembly process for assembly programs.

Thava Kumar A/L Devanayagam

121

Compilation process for java programs.

Thava Kumar A/L Devanayagam

122

Assembly Language Instructions


1. Instruction formats
2. Instruction Types
Data Transfer Instructions

Data Operation Instructions


Program Control Instructions

3. Data Types 4. Addressing Modes


Thava Kumar A/L Devanayagam 123

Instruction Formats
Three-operand instruction
- the op code and three operands.

Two-operand instruction
-the first operand is both destination and one of the source register.

Instruction Formats

Thava Kumar A/L Devanayagam

124

Instruction Formats
One-operand instruction
- the accumulator register is always the destination and one of the source register.

Zero-operand instruction
- all operands are drawn from the stack.

Instruction Formats

Thava Kumar A/L Devanayagam

125

Instruction Types
Data Transfer Instructions
-Move data from one place to another
Load data from memory into the microprocessor.

Store data from the microprocessor into memory.


Move data within the microprocessor

Input data to the microprocessor


Output data from the microprocessor.
Thava kumar A/L Devanayagam 126

Data Transfer Instructions


The data transfer instructions copy data from a source into a destination without modifying the contents of the source. The previous contents of the destination are replaced by the contents of the source.

Thava kumar A/L Devanayagam

127

Data Transfer Instructions


Immediate data transfer Direct data transfer Indirect data transfer Register data transfer Stack data transfer Illustrative Programs

Thava kumar A/L Devanayagam

128

Data Transfer Instructions

Thava kumar A/L Devanayagam

129

Immediate Data Transfer Instructions

The memory location, which is indirectly addressed by the HL register pair, appears as the letter M in all instructions.
Thava kumar A/L Devanayagam 130

Immediate Data Transfer Instructions

Thava kumar A/L Devanayagam

131

Thava kumar A/L Devanayagam

132

Direct Data Transfer Instructions


Direct data transfer instructions are useful if only one byte or word of data is transferred to or from the memory. If more than one byte or word is transferred, it is more efficient to use indirectly addressed instruction.

Thava kumar A/L Devanayagam

133

Direct Data Transfer Instructions

Thava kumar A/L Devanayagam

134

Direct Data Transfer Instructions

Thava kumar A/L Devanayagam

135

Direct Data Transfer Instructions

Copies the contents of location 1000H into the L register and the contents of location 1001 H into the H register

stores the contents of the L register at memory location I200H and the H register at location 1201H
136

Thava kumar A/L Devanayagam

INDIRECT DATA TRANSFER INSTRUCTIONS


With register indirect addressing, a register pair holds the address of the memory location accessed by the instruction. The contents of the register pair indirectly addresses a memory location. Whenever, the letter M appears instead of a register, the HL register pair indirectly addresses a memory location.

Thava kumar A/L Devanayagam

137

INDIRECT DATA TRANSFER INSTRUCTIONS

Thava kumar A/L Devanayagam

138

INDIRECT DATA TRANSFER INSTRUCTIONS

Thava kumar A/L Devanayagam

139

REGISTER DATA TRANSFER INSTRUCTIONS

Thava kumar A/L Devanayagam

140

REGISTER DATA TRANSFER INSTRUCTIONS

Thava kumar A/L Devanayagam

141

STACK DATA TRANSFER INSTRUCTIONS


The Intel 8085A microprocessor has a LIFO (last-in, firstout) stack memory. The stack memory stores both return addresses from subroutines and data temporarily. The microprocessor cannot locate the stack memory when power is first applied to the system because the number in the SP is unknown. The location of the stack must be initialised after the application of system power.

Thava kumar A/L Devanayagam

142

STACK DATA TRANSFER INSTRUCTIONS

The programmer decides what portion of the read/write memory is to function as the stack, and then loads the SP with the top location plus one byte. The byte location above the stack is never used, but must be the initial value of the stack pointer. The SP always points to the current exit point. The stack is a LIFO stack.
Thava kumar A/L Devanayagam 143

STACK DATA TRANSFER INSTRUCTIONS


If data are pushed (placed) onto the stack, they move into the memory locations addressed by SP-1 and SP-2. Note that pairs of registers always move to the stack. A PUSH instruction stores the high-order register first (SP - 1), followed by the low-order register (SP -2). The SP then decrements by two so that the next push occurs below the first. Notice that when the PUSH occurs, nothing is placed at the location addressed by the stack pointer. This is why the SP is initialised at one byte above the top of the stack.
Thava kumar A/L Devanayagam 144

STACK DATA TRANSFER INSTRUCTIONS

Thava kumar A/L Devanayagam

145

STACK DATA TRANSFER INSTRUCTIONS

Thava kumar A/L Devanayagam

146

STACK DATA TRANSFER INSTRUCTIONS


It is also important to note that PUSHes and POPs must occur in pairs: one PUSH, one POP, two PUSHes, two POPs, and so on.

Note: POP PSW will copy the data from location pointed by SP into flag register and data from (SP+1) will copy into A. The SP=SP+2.
Thava kumar A/L Devanayagam 147

STACK POINTER (PENUNJUK TINDAN)


Merupakan daftar 16 bit yang terdapat di dalam sistem mikropemproses yang bertanda SP. Ia digunakan untuk menunjukkan tempat teratas di dalam kawasan tindanan. Ianya betindak sebagai daftar alamat bagi ingatan yang dikhaskan. Untuk melaksanakan tindan, ia perlu diisytiharkan di alamat paling bawah RAM.
Thava kumar A/L Devanayagam 148

Ia juga merupakan suatu kawasan dalam memori (kebiasaannya RAM) di mana data atau alamat akan disimpan semasa mikropemproses melaksanakan salah satu daripada 3 perkara berikut: i. Semasa mikropemproses melaksanakan arahan PUSH dan POP. ii. Apabila mikropemroses melaksanakan arahan jump to subroutine: CALL dan RET) iii. Bila ada interrupt kepada mikropemproses.

Thava kumar A/L Devanayagam

149

TAKRIFAN Struktur data diambil dengan turutan (tindanan) berlawanan dengan turutan semasa menyimpan (last-in-first-out LIFO)
GAMBARAJAH BLOK
Last In In Plate6
Plate6 Plate5 Plate4 Plate3 Plate2 Plate1 Plate6 Plate5 Plate4 Plate3 Plate2 Plate1

Out Plate-6 First Out

Out Plate-5
Plate5 Plate4 Plate3 Plate2 Plate1

In Plate1

In Plate2
Plate2 Plate1

Out Plate-1

Plate1

Plate1

In Plates

Out Plates

Thava kumar A/L Devanayagam

150

JENIS-JENIS TINDAN
LIFO Last In First Out Data yang disimpan (PUSH) kemudian, akan dikeluarkan terdahulu (POP) First In First Out Data yang mula disimpan (PUSH), akan dikeluarkan (POP) terdahulu.

FIFO

Thava kumar A/L Devanayagam

151

Operasi PUSH dan POP dilakukan ke atas kandungan daftar iaitu BC, DE atau HL. Suruhan PUSH dan POP tidak akan menyebabkan sebarang perubahan pada daftar bendera/status. Suruhan PUSH dan POP adalah suruhan 16 bit (2 byte) Semasa operasi PUSH, SP akan berkurangan sebanyal 02H dan kandungan pasangan daftar akan disimpan ke dalam tindan. Semasa operasi POP, kandungan tindan akan dimuatkan ke dlm pasangan daftar dan penunjuk tindan akan bertambah sebanyak 02H.

Thava kumar A/L Devanayagam

152

Contoh: Suruhan PUSH B bermakna daftar B dan C akan disimpan ke dalam tindan. ((SP))-1) <= (B) ((SP))-2) <= (C) (SP) <= (SP)-2)

Thava kumar A/L Devanayagam

153

Contoh: Suruhan POP D bermakna kandungan tindan dimasukkan ke dalam daftar D dan E (E) <= ((SP)) (D) <= ((SP) + 1) (SP) <= (SP) + 2)
Thava kumar A/L Devanayagam 154

FIRST IN FIRST OUT POP MVI B, A6H ; MVI C, 5AH; PUSH B ; POP D; hlt FFF0 FFEF FFEE FFEE FFEF FFF0 PUSH
Thava kumar A/L Devanayagam 155

5A A6 5A A6

E D C B

Illustrative Program: Data Transfer

Thava kumar A/L Devanayagam

156

Illustrative Program: Data Transfer

Thava kumar A/L Devanayagam

157

Illustrative Program: Data Transfer

Thava kumar A/L Devanayagam

158

EXAMPLE 1
Load the accumulator A with the data byte 82H (the letter H indicates hexadecimal number), and save the data in register B. Instructions: MVI A, 82H, MOV B,A

The first instruction is a 2-byte instruction that loads the accumulator with the data byte 82H, and the second instruction MOV B,A copies the contents of the accumulator in register B without changing the contents of the accumulator.
Thava kumar A/L Devanayagam 159

MISCELLANEOUS DATA TRANSFER INSTRUQTIONS


Exchange DE with HL (XCHG)
The XCHG instruction exchanges the contents of the HL register pair with the contents of the DE register pair.

Load SP from HL (SPHL)


Is a one-byte instruction, copies the contents of the HL register pair into the SP.

Exchange HL with Stack Data (XTHL)


This instruction exchanges the contents of the HL pair with the most recent data on the stack.

Input/Output Data Transfer Instructions


IN : instruction inputs data from an I/O device into the accumulator. OUT : sends accumulator data out to an I/O device.
Thava kumar A/L Devanayagam 160

Instruction Types
Data Operation Instructions
-modify their values.
Arithmetic instructions:add, subtract,multiply, divide, clear.

floating point Instructions.


Logic Instructions:AND, OR, XOR,complement.

Shift Instructions:left shift,right shift,rotate.


Thava kumar A/L Devanayagam 161

Data Operation Instructions


Arithmetic Instructions
Addition, subtraction, increment, and decrement.

Thava kumar A/L Devanayagam

162

Arithmetic Instructions

Thava kumar A/L Devanayagam

163

Arithmetic Instructions

Thava kumar A/L Devanayagam

164

Arithmetic Instructions

Thava kumar A/L Devanayagam

165

Arithmetic Instructions

Thava kumar A/L Devanayagam

166

ADDITION
Addition takes several forms in the 8085 microprocessor:
8-bit binary, 16-bit binary, and two-digit binary-coded-decimal (BCE)) addition.

Binary addition functions with either signed or unsigned numbers; BCD addition uses only unsigned numbers. The instruction set supports additions using register addressing, register indirect addressing, and immediate addressing, but not direct addressing.
Thava kumar A/L Devanayagam 167

ADDITION

Thava kumar A/L Devanayagam

168

ADDITION

Thava kumar A/L Devanayagam

169

ADDITION

Thava kumar A/L Devanayagam

170

Addition with Carry


Whenever large numbers (numbers wider than 8 bits, or multiple-byte numbers) are added, the carry must be propagated from one 8-bit segment to the next.

Thava kumar A/L Devanayagam

171

Addition with Carry

Thava kumar A/L Devanayagam

172

Example for addition


Suppose that the DE register pair contains a 16-bit number that we must add to the number in the BC register pair. To accomplish this multiple-byte addition, add F and C together and then add D and B together with the carry. The add-with-carry instruction uses the carry from the addition of E and C to generate the correct answer when D and B are added.

Thava kumar A/L Devanayagam

173

Example for addition

Thava kumar A/L Devanayagam

174

Sixteen-Bit Addition
The 8085 instruction set does contain special instructions (DAD) that do 16-bit addition.

Thava kumar A/L Devanayagam

175

BCD Addition
BCD addition is like binary addition except that the numbers range in value only from 0 through 9. A special instruction allows BCD addition by using the standard binary addition (ADD) instructions.
The DAA instruction appears after a BCD addition (with a binary add instruction) to correct the BCD result. The DAA instruction does not convert a binary number to a BCD number.
Thava kumar A/L Devanayagam 176

Example for Sixteen-Bit Addition

Example 5-6 illustrates the summation of the packed BCD numbers 11 and 19. After this addition, the accumulator contains a 2AH, which is not a BCD number:
the answer should be a 30BCD The DAA instruction corrects the answer after the addition and provides a 30BCD after the DAA instruction executes.
Thava kumar A/L Devanayagam 177

BCD Addition
The DAA instruction changes the result through the two tests listed by adding a OOH, 06H, 60H, or 66H to the accumulator.
If the least significant half-byte is greater than 9 or if the AC flag = 1, the DAA instruction adds a 06H to the accumulator. If the most significant half-byte is greater than 9 or if the C flag bit 1, the DAA instruction adds a 60H to the accumulator.

Thava kumar A/L Devanayagam

178

Increment
The last form of addition is to increment or add 1. The increment command is either an 8-bit (INR) increment or a 16-bit (INX) Increment instruction. The INR instructions affect all the flags except carry, and the INX instructions affect no flags.

Thava kumar A/L Devanayagam

179

Thava kumar A/L Devanayagam

180

Subtraction
The 8085 supports 8-bit binary subtraction and decrement. It also supports a subtraction instruction that allows a borrow to be propagated through additional bytes of a number. The subtract-with-borrow instruction aids in the subtraction of multiple-byte numbers.

Thava kumar A/L Devanayagam

181

Subtraction The 8085 performs subtraction by using the method of 2s complement. Subtraction can be performed by using either:
the instruction SUB to subtract contents of a source register or the instruction SUI to subtract an 8-bit number from contents of the accumulator. In either case, the accumulator contents are regarded as minuend (the number from which to subtract).
Thava kumar A/L Devanayagam 182

Subtraction
Various subtraction instructions: register, register indirect, and immediate addressing. Direct addressing is not allowed for a subtraction. Each of these instructions affects the flag bits, so they reflect various conditions about the difference after a subtraction.

Thava kumar A/L Devanayagam

183

Subtraction
The 8085 performs the following steps internally to execute the instruction SUB (or SUI):
Converts subtrahend (the number to be subtracted) into its 1s complement. Adds 1I to 1s complement to obtain 2s complement of the subtrahend. Add 2s complement to the minuend (the contents of the accumulator). Complements the Carry flag.

Thava kumar A/L Devanayagam

184

Illustrative Program: Subtraction of Two Numbers

PROBLEM STATEMENT
Write a program to do the following:
Load the number 3011 in register B and 3911 in register C. Subtract 39H from 3011. Display the answer at PORT I.

Thava kumar A/L Devanayagam

185

Illustrative Program: Subtraction of Two Numbers

Thava kumar A/L Devanayagam

186

Illustrative Program: Subtraction of Two Numbers

PROGRAM DESCRIPTION
Registers B and C are loaded with 30H and 39H, respectively. The instruction MOV A,B copies 30H into the accumulator (shown as register contents).

Thava kumar A/L Devanayagam

187

Illustrative Program: Subtraction of Two Numbers


To

execute the instruction SUB C the microprocessor performs the following steps internally:

Thava kumar A/L Devanayagam

188

Illustrative Program: Subtraction of Two Numbers

PROGRAM DESCRIPTION
The number F7H is a 2s complement of the magnitude (39H-30H)=09H.
This Cy flag is set, indicating the answer is in 2s complement.

The instruction OUT displays F7 at PORT1.

Thava kumar A/L Devanayagam

189

Subtraction

P= 0

Odd parity

Thava kumar A/L Devanayagam

190

Subtract with Borrow

Thava kumar A/L Devanayagam

191

Subtract with Borrow

Thava kumar A/L Devanayagam

192

Example for Subtraction


Suppose that the number in the DE pair must be subtracted from the BC pair. The least significant is operated on first. Once the difference of C and E is found, the D register is subtracted from the B register with a borrow. The subtraction with borrow effectively propagates the borrow through the most significant byte of the result.

Thava kumar A/L Devanayagam

193

LOGIC INSTRUCTIONS
Four basic logic functions: invert, AND, OR, and exclusive-OR. Why does a microprocessor instruction set contain logic instructions? Logic instructions sometimes replace discrete logic gates. Today, program storage costs about of a cent per byte. System control software usually requires bit manipulation a logic operation.

Thava kumar A/L Devanayagam

194

Inversion (NOT)
The CMA instruction (2FH in machine language), onescomplements or inverts the contents of the accumulator. This operation, which affects none of the flag bits, causes each bit of the accumulator to be inverted (changed from 1 to 0 or 0 to 1). The CMA instruction causes the accumulator to appear as eight inverters (or NOT).
This means that this one-byte instruction replaces eight discrete inverters if the speed required is not too great. The amount of circuitry replaced by the CMA instruction is 14 of a 7404 TTL hex inverter.

Thava kumar A/L Devanayagam

195

The AND Operation


The AND instruction, has two separate functions in a microprocessor-based system.
The AND instruction selectively clears bits of the accumulator or replaces discrete AND gates.

The AND instruction, functions as eight independent twoinput AND gates. This instruction replaces two 7408 quad two-input AND gates.

Thava kumar A/L Devanayagam

196

The AND Operation

Thava kumar A/L Devanayagam

197

The AND Operation

Thava kumar A/L Devanayagam

198

The OR Operation
Has two separate functions in a microprocessor-based system:
It selectively sets bits of the accumulator or Replaces discrete OR gates.

The inclusive-OR instruction functions as eight independent two-input OR gates. This instruction replaces two 7432 quad two-input OR gates.

Thava kumar A/L Devanayagam

199

The OR Operation

Thava kumar A/L Devanayagam

200

The OR Operation

Thava kumar A/L Devanayagam

201

Thava kumar A/L Devanayagam

202

Illustrative Program: ORing Data from Two Input Ports

PROBLEM STATEMENT
Two input port with eight switches (each port) at address 00H and OIH (Figure 6.9) is connected to the microcomputer to control the same appliances and lights from the bedroom as well as from the kitchen. Write instructions to turn on the devices from any of the input ports.

Thava kumar A/L Devanayagam

203

Illustrative Program: ORing Data from Two Input Ports

Thava kumar A/L Devanayagam

204

Illustrative Program:
ORing Data from Two Input Ports

PROBLEM ANALYSIS
To turn on the appliances from any one of the input ports, the microprocessor needs to read the switches at both ports and logically OR the switch positions. Assume that the switch positions in one input port (located in the bedroom) correspond to the data byte 9lH and the switch positions in the second port (located in the kitchen) correspond to the data byte A8H. The person in the bedroom wants to turn on the air conditioner, the radio, and the bedroom light; and the person in the kitchen wants to turn on the air-conditioner, the coffeepot, and the kitchen light. By ORing these two data bytes, the MPU can turn ON the necessary appliances.
Thava kumar A/L Devanayagam 205

Illustrative Program:
ORing Data from Two Input Ports

Thava kumar A/L Devanayagam

206

Exclusive OR (XOR)

Thava kumar A/L Devanayagam

207

ROTATE INSTRUCTIONS

Thava kumar A/L Devanayagam

208

SHIFT INSTRUCTIONS

Thava kumar A/L Devanayagam

209

Instruction Types
Program Control Instructions
Jump/branch instruction similar to GOTO
-absolute(always taken)/conditional

Software interrupts are generated by specific instructions.


Hardware interrupts are triggered by device outside of the microprocessor. Exceptions/traps are triggered by invalid operation,e.g.:dividing by zero.
Thava kumar A/L Devanayagam 210

Branching Instructions Jump Instructions: JMP 16-bit There are some conditional jump instructions Call and Return: CALL 16-bit RET There are some conditional jump instructions Restart Instructions:
Machine Control Instructions HLT NOP
Thava kumar A/L Devanayagam 211

Branching Instructions
the 8085 code to perform this algorithm MVI MOV XRA Loop: ADD DCR JNZ STA A,5 B,A A B B Loop 2000

sum=A A=0 sum=sum+i i=i-1 IF in THEN GOTO Loop total=sum

Thava kumar A/L Devanayagam

212

Branching Instructions
Execution trace of the 8085 loop summation

Thava kumar A/L Devanayagam

213

Control Instructions
Allow computers to make decisions and change the flow of the programme based on the results outcome. Two main forms:
JUMP instructions:
Allow programme to jump to any memory locations.

CALL instructions
Allow a group of instructions (subroutine) to be reused by the program in many different places.
Thava kumar A/L Devanayagam 214

CONDITIONAL JUMP
Conditional JUMP instructions:
Allow the programmer or programme to make a choice based on conditional terms. A condition is tested by the microprocessor to decide whether a jump occurs. The conditions tested by the conditional jumps are the same conditions held in the flag bits. The terms are :
Zero / not zero Carry set / cleared Positive / minus Parity odd / even
Thava kumar A/L Devanayagam 215

CONDITIONAL JUMP INSTRUCTIONS

Thava kumar A/L Devanayagam

216

CONDITIONAL JUMP INSTRUCTIONS

Thava kumar A/L Devanayagam

217

CONDITIONAL JUMP INSTRUCTIONS

Thava kumar A/L Devanayagam

218

SUBROUTINES
A subroutine is a short sequence of instructions that performs a single task. One advantage of using a subroutine is a significant savings of memory space. Subroutines also simplify the task of writing a program because subroutines only appear in a program once, but are used often. CALL instruction allows the programmer to use (link to) a subroutine. When the 8O85 executes a CALL instruction, two events occur: The contents of the PC are pushed onto the stack, and The program continues at the address stored with the CALL instruction. The CALL instruction is a combination of the PUSH and the JMP instructions.

Thava kumar A/L Devanayagam

219

SUBROUTINES

Thava kumar A/L Devanayagam

220

SUBROUTINES
The RET(return) instruction returns to the main program at the instruction that follows the CALL. This can be accomplished because the address of this instruction is stored on the stack because the CALL placed it there as a return address. The RET command POPs a number from the stack and places it into the program counter.

Thava kumar A/L Devanayagam

221

Note: Let initial SP=1000H

SUBROUTINES

STACK(before) CALL COMP


1000

? ?
AFTER CALL COMP STACK

20 05
REGISTERS

FFFF

FFFE

01

PC 2040 SP FFFE
Thava kumar A/L Devanayagam 222

Instruction Size
1-byte instructions: Opcode and operand in the same byte. MOV C,A Opcode= Hex code = 4FH ADD B

2-byte instructions: First byte = Opcode; Second byte = Operand; MVI A,32H Opcode= Hex code = 3EH = 1st byte; 32H = 2nd byte 3-byte instructions: First byte = Opcode; Second byte = Low order address; Third byte = High order address JMP 3035H Opcode= Hex code = C3H = 1st byte; 35H = 2nd byte; 30H = 3rd byte.
Thava kumar A/L Devanayagam 223

Some Important Symbols


R = 8-85 8-bit registers (A, B, C, D, E, H, L) M = Memory register (location) Rs = Register source (A, B, C, D, E, H, L) Rd = Register destination (A, B, C, D, E, H, L) Rp = Register pair (BC, DE, HL, SP) ( ) = Contents of --Note: The microprocessor interprets the first byte as an opcode and after decoding the opcode it comes to know about the next operation to be performed.
Thava kumar A/L Devanayagam 224

Chapter 4
MOD-MOD PENGALAMATAN & TEKNIK PENGATURCARAAN Addressing Modes & Programming technique

Thava kumar A/L Devanayagam

225

Definition
The procedure of fetching and sending data between source and destinations is carried out by various addressing approaches

Thava kumar A/L Devanayagam

226

Microprocessor needs memory address to access data from the memory. Assembly language may use several addressing modes to implement this task.

Thava kumar A/L Devanayagam

227

ADDRESSING MODES OF 8085


There are 5 addressing mode
Register addressing mode Direct addressing mode Register Indirect addressing mode Immediate addressing mode Implicit addressing mode

Thava kumar A/L Devanayagam

228

ADDRESSING MODES OF 8085


There are three other very important addressing mode which exist in other microprocessors and are not available in 8085. They are
Indirect Addressing mode Index addressing mode Relative addressing mode

However this addressing mode can be realized in 8085 by combinations of instructions


Thava kumar A/L Devanayagam 229

ADDRESSING MODES OF 8085


Immediate addressing:
Immediate data is transferred to address or register. Example: MVI A,20H. Transfer immediate data 20H to accumulator. Number of bytes: Either 2 or 3 bytes long. 1st byte is opcode. 2nd byte 8 bit data . 3rd byte higher byte data of 16 bytes.
Thava kumar A/L Devanayagam 230

ADDRESSING MODES OF 8085


Register addressing:
Data is transferred from one register to other. Example: MOV A, C :Transfer data from C register to accumulator. Number of bytes: Only 1 byte long. One byte is opcode.

Thava kumar A/L Devanayagam

231

ADDRESSING MODES OF 8085


Direct addressing:
Data is transferred from direct address to other register or vice-versa. Example: LDA C200H .Transfer contents from C200H to Acc. Number of bytes: These are 3 bytes long. 1st byte is opcode. 2nd byte lower address. 3rd byte higher address.

Thava kumar A/L Devanayagam

232

ADDRESSING MODES OF 8085


Indirect addressing:
Data is transferred from address pointed by the data in a register to other register or vice-versa. Example: MOV A, M: Move contents from address pointed by M to Acc. Number of bytes: These are 3 bytes long. 1st byte is opcode. 2nd byte lower address. 3rd byte higher address.
Thava kumar A/L Devanayagam 233

ADDRESSING MODES OF 8085


Implicit addressing:
These doesnt require any operand. The data is specified in Opcode itself. Example: RAL: Rotate left with carry.
RRC- rotate accumulator content with out carry No.of Bytes: These are single byte instruction or Opcode only.

Thava kumar A/L Devanayagam

234

Assembly Language
Assembly language: Assembly language is used for most programming because it is extremely difficult to program a microprocessor in its native, that is hexadecimal machine language. Assembler: An assembler is a program that converts software written in symbolic machine language (the source programme) into hexadecimal machine language (object programme). The primary reason to use assembler is because development and modification are always difficult in machine language.
Thava kumar A/L Devanayagam 235

Assembly Language
The Two-pass Assembler : Read programme two times.
1. Generate a table of the labels/symbols within the source programme. 2. Develop hexadecimal version of the source programme.

Allow forward addressing (the software can jump ahead to an instruction in a program).

Thava kumar A/L Devanayagam

236

Assembly Language

Thava kumar A/L Devanayagam

237

Assembly Language
The assembler always assumes that the first instruction of the programme is stored at memory address 0000H unless otherwise directed by the ORG command.

Thava kumar A/L Devanayagam

238

Assembly Language
Pass One:
The assembler scans the source programme during the first pass and generates a table of the labels found within the source programme. Each entry in the label table contains the label and the address where the label appears in the programme. During the first pass the assembler determines the length of each instruction by updating an internal programme counter. This internal programme counter allows the assembler to complete the label table by equating each label with the counter. Once the label table is complete the second pass begin.
Thava kumar A/L Devanayagam 239

Assembly Language
Pass Two: During the second pass of the source programme, the assembler forms the object programme. This occurs by referring to the label table for any labels that appear in the programme and to an instruction table. The instruction table contains all the opcodes in both symbolic and machine language forms. The tables help convert the source programme into the object programme.
Thava kumar A/L Devanayagam 240

Assembly Language

Thava kumar A/L Devanayagam

241

Assembly Language
Assembly Language Statement: Format :

Label Field. Contains a symbolic memory address that refers to the statement in a programme. Labels are optional and must end with a colon in some Intel 8085A ( : ). Labels are constructed from alphanumeric characters and must begin with any letter of the alphabet. Thava kumar A/L Devanayagam 242

Assembly Language

Thava kumar A/L Devanayagam

243

Assembly Language
Opcode field:
This field must contain opcodes.

Operand field:
May contain register name, data or labels. If more than one of these is present, they must be separated with comma. Data must be encoded as decimal, binary, octal, hexadecimal, or ASCII. ASCII must appear as one of more letters surrounded by apostrophe.

Thava kumar A/L Devanayagam

244

Assembly Language
Operand arithmetic operations.

Thava kumar A/L Devanayagam

245

Assembly Language
Comment field. Must begin with semicolon in most 8085 assemblers and may continue to the end of the line only. Use asterisk * or semicolon ; if the comment should continue into the next line. Example :

Thava kumar A/L Devanayagam

246

Assembly Language
Assembler pseudo operations. Directives to the assembler programme that may or may not generate machine code. Examples :
END, DB, DW, DS, ORG, EQU, IF, ENDIF, SET, GLB, EXT, TITLE, SPC.

All pseudo operations must appear in the opcode field of a statement.

Thava kumar A/L Devanayagam

247

Assembly Language
Define Byte (DB). Defines 8-bit memory data for a programme. Multiple one byte data, comma ( , ) as a separator.

Thava kumar A/L Devanayagam

248

Assembly Language : Example

Thava kumar A/L Devanayagam

249

Assembly Language
Origin (ORG). Changes the starting location of the programme to another address besides 0000H. Can be used at any place in a programme to change the location of the assembled machine language instructions or data.
Thava kumar A/L Devanayagam 250

Assembly Language : Example

Thava kumar A/L Devanayagam

251

Assembly Language
Define Word (DW). Pseudo operation stores a 16-bit number in the memory for use by a programme. Defines no only numeric data but also memory addresses and label.

Thava kumar A/L Devanayagam

252

Assembly Language : Example

Thava kumar A/L Devanayagam

253

Assembly Language
Define Storage (DS). Reserves space in a programme for variable data. Does not place any specific data into the reserved area of memory.

Thava kumar A/L Devanayagam

254

Assembly Language : Example

Thava kumar A/L Devanayagam

255

Assembly Language
Equate (Equ). Equates a label to another label or value. Note that the EQU statement label does not contain a colon ( : ).

Thava kumar A/L Devanayagam

256

Assembly Language

Thava kumar A/L Devanayagam

257

Structured Assembly Language Programming


What is structured assembly language programming ? It is a programming methodology that aids in the development of complicated software with a minimum amount of error.

Thava kumar A/L Devanayagam

258

Flow Chart
Flow chart is a flow design structured programme to solve the problems. Flow chart also helps to correct and modify developed software. There are symbols to use in designing flow chart to ease programmer. These symbols consists of following process:
Process, predefined process, input/output, decision, connector and terminal.

Table shows examples of symbols to use in flow chart programme.


Thava kumar A/L Devanayagam 259

Thava kumar A/L Devanayagam

260

Structured Assembly Language Programming


Process Symbol: Shows any type of process in a programme. Predefined process: Usually contains the name of the subroutine or module. Input / output symbol: Whenever data are input to the programme or output from the programme. The input / output symbol usually shows the type of data and the directioin of data flow. Decision symbol: Computer systemss most capability is ability to make decisions. The symbol asks question to determine the direction of programme sequence.
Thava kumar A/L Devanayagam 261

Structured Assembly Language Programming

Connector: Eliminates crisscrossed connecting lines in complicated flowcharts. Ease in understanding the developed programme. Terminal Symbol: Programmes all start somewhere and require a symbol to show where they start.

Thava kumar A/L Devanayagam

262

Flow chart
Flow chart example: mean calculation of a set of numbers

Thava kumar A/L Devanayagam

263

If-Then-Else

Thava kumar A/L Devanayagam

264

If-Then-Else
The solution.

Thava kumar A/L Devanayagam

265

Repeat-Until
Allows process to be executed or repeated until an event occurs. Whenever this construct appears, the process first executes a task and then a test checks for a true or a false condition. The following figures shows the repeat-until-true and repeat-until-false.

Thava kumar A/L Devanayagam

266

Repeat-Until: Example
Reads the keyboard until a CR (carriage return) is detected.

Thava kumar A/L Devanayagam

267

Do-While
Is comparable to the repeat-until except for one basic difference.
The do-while construct checks the condition and then, if required, performs the process and repeats the check. There are two forms: do-while-false and do-while-true.

Thava kumar A/L Devanayagam

268

Do-While

Thava kumar A/L Devanayagam

269

PENERANGAN LANGKAHLANGKAH PROGRAM


1. DEFINISI MASALAH
Pengaturcara hendaklah mengetahui tujuan khusus untuk membina aturcara yang hendak dihasilkan iaitu apakah masalah yang hendak diselesaikan. Faktor yang perlu diambil kira: 1. Jenis keluaran yang diperlukan 2. Perkakasan yang ada 3. Bahasa pengaturacaraan yang hendak digunakan 4. Kekangan yang ada

2. MEREKEBENTUK Merekabentuk aturcara yang hendak ditulis, sama ada dalam bentuk algoritma LOGIKAL

atau secara grafik dalam bentuk carta alir.

Thava kumar A/L Devanayagam

270

3. PENGATURCARAAN

Dgn bantuan algoritma dan carta alir, penulis boleh mula menulis aturcara yang diperlukan dengan menggunakan penyunting (text editor) untuk bahasa penghimpun atau secara terus untuk bahasa tahap tinggi. Aturcara ini adalah aturcara punca (source program) Contoh program :

Thava kumar A/L Devanayagam

271

4.

MUAT TURUN (LOADING), MENGUJI (TESTING) & NYAHPEPIJAT (DEBUGGING)

Penghimpun (assembler) akan menghimpunkan aturcara bahasa penghimpun. Penghimpun akan mengeluarkan fail senarai (list file) yang digunakan untuk mencari kesilapan di peringkat ini. Bagi bahasa tahap tinggi, pengkompil dan pentafsir akan menyatakan sebarang kesilapan yang telah dilakukan. Kesilapan atau error biasanya ralat sintaks iaitu penggunaan bahasa pengaturcaraan yang salah Jika tiada ralat, penghimpun akan mengeluarkan fail objek dan fail heksadesimal. Jika tiada ralat sintaks, aturcara boleh dijalankan untuk mengesan ralat logikal atau ralat semantik. Ralat logikal adalah kesilapan yang menyebabkan aturcara yang tidak berfungsi seperti yang dikehendaki iaitu tidak menepati tujuan yang ditetapkan.
Thava kumar A/L Devanayagam 272

Contohnya suatu aturcara ditulis untuk mengira markah penilaian pelajar di dalam kelas. Namun, aturcara yang ditulis tidak dapat mengira dengan tepat, maka aturcara ini ada ralat logikal iaitu penggunaan bahasa pengaturcaraan yang betul tetapi fungsinya tidak tepat. Jika ini berlaku, pengaturcara perlu kembali ke langkah yang kedua (merekabentuk logikal) dan mengulangi prosesproses seterusnya hingga aturcara beroperasi seperti yang dikehendaki. Proses pencarian ralat ini juga dikenali proses nyahpepijat atau debugging. Bg bhs penghimpun, pengujian boleh dilakukan dengan memuat-turunkan (download) aturcara tersebut pada simulator.

5.

Pengaturcara boleh mencetak aturcara fail punca DOKUMENTA sebagai dokumentasi dan mencatat komen yang SI PROGRAM sesuai pada aturcara sebagai panduan kepada pengguna lain.
Thava kumar A/L Devanayagam 273

LOOPING
The programming technique used to instruct the MPU to repeat task. Continuous loop Conditional loop
Repeat task until certain conditions are met.

Some loop include indexing along with counter. Indexing: pointing or referencing objects with sequential numbers, i.e. data in memory are accessed by referencing to their memory locations.
Thava kumar A/L Devanayagam 274

COUNTER
Counter. Counter is constructed by loading a number to any register. Then use INR or DCR to increment or decrement the number respectively. Loop is used to update counter value and every iteration the number is inspected to check whether the number is at maximum or Thava kumar A/L Devanayagam minimum.

275

BLOCK DATA TRANSFERS


In many systems, blocks of information are transferred from one place to another in the microprocessors memory. Transferring Blocks of Bytes. Transferring Blocks of Words.

Thava kumar A/L Devanayagam

276

BLOCK DATA TRANSFERS


Suppose that a block of 10 bytes of data, beginning at memory location 2080H, is transferred to a block of memory beginning at location 2090H.
The simplest method, is to use the LDA and STA instruction to transfer each byte.
Long program

A more efficient way to transfer a block of data uses the programmed-loop and counter.
Thava kumar A/L Devanayagam 277

Flowchart
Flowchart required to transfer a block of bytes from one area of memory to another .

Thava kumar A/L Devanayagam

278

Transfer 10 bytes of data

Thava kumar A/L Devanayagam

279

Chapter 5
SISTEM INGATAN Memory System

Thava kumar A/L Devanayagam

280

SISTEM INGATAN
Ingatan adalah peranti yang digunakan untuk menyimpan data dan maklumat. Merupakan salah satu peranti yang penting didalam sistem komputer. Data yang disimpan didalam sistem ingatan berbentuk nombor perduaan iaitu '0' atau '1'. Jenis ingatan dalam sistem ingatan ialah ingatan semikonduktor (separa pengalir) Ingatan semikonduktor mempunyai masa capaian yang pendek berbanding dengan jenis ingatan lain. Sesuai digunakan didalam sistem mikropemproses untuk operasi kerja pantas

Thava kumar A/L Devanayagam

281

Kategori ingatan
Data digit boleh disimpan sebagai cas dalam kapasitans dan sejenis ingatan separa pengalir yang penting menggunakan prinsip bagi mendapatkan simpanan ketumpatan tinggi pada aras keperluan kuasa rendah. Ingatan utama juga dikenali sebagai ingatan bekerja yang saling bertindak balas dengan CPU. Ingatan Bantu adalah mempunyai muatan untuk simpan jumlah data yang banyak tanpa memerlukan kuasa elektrik yang berkelajuan rendah seperti CD,disket.
Thava kumar A/L Devanayagam 282

MEMORI DLM SISTEM KOMPUTER


KOMPUTER
Internal Memory MEMORI (semiconductor) DALAMAN

Arithmetic unit UNIT

ALU

KAWALAN

Control Unit UNIT

(semiconductor)

Auxiliary mass strorage (tape, disk, MBM)

Thava kumar A/L Devanayagam

283

PERBEZAAN
Memori

INGATAN UTAMA
Memori dalaman komputer

INGATAN KEDUA
Memori luaran komputer

Menyimpan

Program Boot up (BIOS) Program dan data tidak dikendalikan oleh CPU, hanya berlaku permindahan bila diperlukan. Perisian aplikasi seperti Microsoft Word.
RAM and ROM floppy disk CDROM magnetic disk/tape.

Contoh

Thava kumar A/L Devanayagam

284

MEMORI SEMIKONDUKTOR

ROM

RAM

PROGRAMABLE

ERASABLE PROGRAMABLE (RMM) PROM

SRAM

DRAM

MROM

UV

ERASABLE

ELECTRIC ERASABLE

EPROM
EEPROM

EAROM

Thava kumar A/L Devanayagam

285

Nonvolatile Memories
Nonvolatile memories retain value even if powered off. Generic name is read-only memory (ROM). Misleading because some ROMs can be read and modified. Types of ROMs Programmable ROM (PROM) Erasable programmable ROM (EPROM) Electrically erasable PROM (EEPROM) Flash memory Firmware Program stored in a ROM Boot time code, BIOS (basic input/ouput system) graphics cards, disk controllers.

Thava kumar A/L Devanayagam

286

JENIS-JENIS ROM
ROM ( Read Only Memory )
PROM (Programmable Read Only Memory) EPROM (Erasable Programmable Read Only Memory) EEPROM (Electrically Erasable Programmable Read Only Memory)

Thava kumar A/L Devanayagam

287

INGATAN BACA SAHAJA (ROM)


Ingatan untuk tempat simpanan kekal dimana datanya hanya boleh dibaca sahaja dari lokasi. Menyimpan satu bit dengan adanya ikatan di antara talian baris dan talian lajur didalam susunan ingatan. Data didalam ROM biasanya telah diaturcarakan pada masa pengilangan ataupun dengan satu kaedah aturcara sebelum pemasangan litar. ROM bersifat 'Non-Volotile' (tak meruap) dimana aturcara ini tidak akan berubah (padam/hilang) walaupun bekalan kuasa diputuskan. ROM sesuai digunakan untuk menyimpan data atau maklumat penting seperti operasian sisitem ( operating system )
Thava kumar A/L Devanayagam 288

PROM (Programmable ROM)

PROM
Diatur cara Keburukan

Kait boleh lakur


oleh pengguna, tidak bg pengilang Sekali diaturcara (OTP) Tidak boleh dipadam atau diatur cara semula
dibuat dari 1 fius kait nipis yang sedia tersambung oleh pengilang bakar fius bagi menghasilkan data ingatan tersimpan yang dikehendaki: . Hubungkan alamat pada alamat masukan . letakkan data yang dikehendaki pada pin data . Vpp/Vdd pada nilai tinggi (10-30V)
Thava kumar A/L Devanayagam 289

Setiap sambungan

( Sumber: Sistem Digit: Ronald A. Reis; m/s 631; rajah 11.9)

Thava kumar A/L Devanayagam

290

PERBEZAAN
Ingatan Baca

EPROM
Yang boleh diaturcara dan dipadam menggunakan EPROM eraser (didedahkan kepada cahaya ultraviolet selama 12 minit atau dijemur di bawah sinaran matahari selama 1 hari)

EEPROM
Yang boleh diaturcara dan dipadam menggunakan isyarat (denyut) elektrik.Proses hanya 10ms

Pengguna

Tidak boleh memilih untuk memadamkan kandungan tertentu sahaja (boleh mempengaruhi bahagian lain)
Mesti dikeluarkan dari litar untuk diaturcara semula Di dlm makmal pembangunan produk, makmal kajian (research & development) dan dalam penghasilan prototaip.
Thava kumar A/L Devanayagam

Boleh memilih lokasi tertentu sahaja untuk dipadamkan tanpa mempengaruhi bahgaian lain.
Tidak perlu dikeluarkan dari litar untuk diaturcara Di dlm BIOS sistem komputer (basic input/ Output system)

Kendalian aturcara Penggunaan secara meluas

291

INGATAN CAPAIAN RAWAK (RAM)


Ingatan untuk tempat simpanan sementara data sebelum diproses dalam sistem mikropemproses. RAM bersifat 'Volotile' (meruap) iatu data yang disimpan didalamnya akan hilang atau rosak sekiranya bekalan kuasa terganggu/terputus. Data pada lokasi/alamat ingatan boleh dicapai secara rawak Operasi tulis boleh dilakukan berulangkali pada lokasi/alamat yang sama dan data sebelumnya terpadam dan data yang baru akan disimpan.

Thava kumar A/L Devanayagam

292

Random-Access Memory (RAM)


Key features RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RAM chips form a memory. Static RAM (SRAM) Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor and transistor. Value must be refreshed every 10-100 ms. Sensitive to disturbances. Slower and cheaper than SRAM.
Thava kumar A/L Devanayagam 293

SRAM vs DRAM Summary


Tran. per bit SRAM DRAM 6 1 Access time Persist? Sensitive? 1X 10X Yes No No Yes

Cost 100x 1X

Applications cache memories Main memories, frame buffers

Thava kumar A/L Devanayagam

294

PERBEZAAN
Sel ingatan terdiri drp

RAM STATIK
flip-flop

RAM DINAMIK
kapasitor

Data

Yang disimpan tidak akan hilang selagi ada bekalan kuasa

Yang disimpan akan hilang walaupun bekalan kuasa masih ada apabila kapasitor dicas. Oleh itu, data perlu direfresh atau dicas semula pada sela masa tertentu
Tinggi- (4 kali ganda SRAM). Saiz unitnya lebih ringkas dan boleh dipadatkan di dalam 1 cip Rendah- (1/6 atau dr kuasa SRAM)

Ketumpatan

Rendah- IC lebih besar

Penggunaan kuasa

Tinggi

Thava kumar A/L Devanayagam

295

PERBEZAAN
Format

RAM STATIK

RAM DINAMIK

Terdapat pelbagai Hanya terdapat dlm 1 format(1 bit, 1 byte, format 1 bit byte)- ini memudahkan sistem ingatan dibina dengan pantas
Kos perbit lebih tinggi Kos perbit rendah (1/4 atau 1/5 kos SRAM) Dalam bentuk cas-cas pada kapasitor Lebih rumit krn memerlukan litar tambahan utk refreshkan data
296

Kos

Maklumat disimpan Dlm bentuk bit-bit pada flip-flop Penggunaan kendalian Lebih mudah digunakan krn tidak memerlukan litar tambahan
Thava kumar A/L Devanayagam

PERBEZAAN
Kepantasan Litar

RAM STATIK
Lebih pantas Tidak kompleks

RAM DINAMIK
sederhana kompleks

Thava kumar A/L Devanayagam

297

Conventional DRAM Organization


d x w DRAM: dw total bits organized as d supercells of size w bits
16 x 8 DRAM chip
cols 0
2 bits /

0 1

addr

rows
memory controller (to CPU)
8 bits /

2 3

supercell (2,1)

data

internal row buffer


Thava kumar A/L Devanayagam 298

Reading DRAM Supercell (2,1)


Step 1(a): Row access strobe (RAS) selects row 2. Step 1(b): Row 2 copied from DRAM array to row buffer.
16 x 8 DRAM chip cols
RAS = 2
2 /

0 0 1

addr memory controller


8 /

rows 2 3

data

internal row buffer


Thava kumar A/L Devanayagam 299

Reading DRAM Supercell (2,1)


Step 2(a): Column access strobe (CAS) selects column 1. Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. 16 x 8 DRAM chip
cols CAS = 1
2 /

0 0 1

To CPU
memory controller supercell (2,1)

addr

rows
2
8 /

3 internal buffer

data

supercell (2,1)

internal row buffer

Memory Modules
addr (row = i, col = j) : supercell (i,j)
DRAM 0

DRAM 7

64 MB memory module consisting of eight 8Mx8 DRAMs

bits bits bits bits bits bits bits 56-63 48-55 40-47 32-39 24-31 16-23 8-15

bits 0-7

63

56 55

48 47

40 39

32 31

24 23 16 15

8 7

64-bit doubleword at main memory address A

Memory controller

64-bit doubleword

Thava kumar A/L Devanayagam

301

Enhanced DRAMs
All enhanced DRAMs are built around the conventional DRAM core. Fast page mode DRAM (FPM DRAM) Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]. Extended data out DRAM (EDO DRAM) Enhanced FPM DRAM with more closely spaced CAS signals. Synchronous DRAM (SDRAM) Driven with rising clock edge instead of asynchronous control signals. Double data-rate synchronous DRAM (DDR SDRAM) Enhancement of SDRAM that uses both clock edges as control signals. Video RAM (VRAM) Like FPM DRAM, but output is produced by shifting row buffer Dual ported (allows concurrent reads and writes)

Thava kumar A/L Devanayagam

302

PERBEZAAN
Data

ROM
Dibaca sahaja

RAM
boleh dibaca atau ditulis. Digunakan bagi menyimpan data secara sementara (ketika CPU memproses).

Penggunaan

Digunakan untuk menyimpan aturcara sistem yang telah di tulis secara kekal dan tidak boleh di ubah.

Jenis ingatan

tidak meruap iaitu kandungannya tidak hilang walaupun bekalan kuasa di putuskan.
Thava kumar A/L Devanayagam

meruap iaitu kandungannya akan hilang bila bekalan kuasa diputuskan.

303

Typical Bus Structure Connecting CPU and Memory


A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices.
CPU chip register file ALU system bus memory bus

bus interface

I/O bridge
Thava kumar A/L Devanayagam

main memory
304

Memory Read Transaction (1)


CPU places address F100 on the memory bus.
register file A ALU main memory 0
x

Load operation: mov M, A

I/O bridge bus interface

F100

F100

Thava kumar A/L Devanayagam

305

Memory Read Transaction (2)


Main memory reads F100 from the memory bus, retreives word x, and places it on the bus.
register file A ALU main memory 0
x

Load operation: mov A, M

I/O bridge bus interface

F100

Thava kumar A/L Devanayagam

306

Memory Read Transaction (3)


CPU read word x from the bus and copies it into register A.
register file A
x

Load operation: mov A , M ALU main memory 0


x

I/O bridge bus interface

F100

Thava kumar A/L Devanayagam

307

Memory Write Transaction (1)

CPU places address F100 on bus. Main memory reads it and waits for the corresponding data word to arrive.
register file ALU main memory 0 F100 Store operation: mov M, r

I/O bridge bus interface

F100

Thava kumar A/L Devanayagam

308

Memory Write Transaction (2)


CPU places data word y on the bus.
register file B
y

Store operation: mov M, r ALU main memory 0 F100

I/O bridge bus interface

Thava kumar A/L Devanayagam

309

Memory Write Transaction (3)

Main memory read data word y from the bus and stores it at address F100.
register file Store operation: mov M, r

ALU
main memory F100 0
y

I/O bridge

bus interface

Thava kumar A/L Devanayagam

310

CONTROL BUS

CS

W/R

RD PROCESSOR

A2 0 0 0

A1 0 0 1

A0 0 1 0

A0

Selected location 0th Location 1st Location

8X8

A1 A2

1 0

1 0

D0
D7

Address bus

D0
D7
1 0 1

Data bus

Thava kumar A/L Devanayagam

311

Interconnection between Processor and Memory


Thava kumar A/L Devanayagam 312

Read Transaction
(PC) (MAR) (MAR)

(Address bus) Select a particular memory location Issues RD control signals Reads instruction present in memory via database Will be placed in IR

Thava kumar A/L Devanayagam

313

Instruction present in IR will be decoded by which processor understand what operation it has to perform
Increments the contents of PC by 1, so that it points to the next instruction address

If data required for operation is available in register, it performs the operation


If data is present in memory following sequence is performed

Thava kumar A/L Devanayagam

314

Write Transaction
Cont:-

Address of the data


MAR RD signal Address bus

MAR select memory location where is issued

Reads data via data bus

MDR

From MDR data can be directly routed to ALU or it can be placed in register and then operation can be performed

Results of the operation can be directed towards output device, memory or register
Thava kumar A/L Devanayagam 315

KITAR AMBIL

1. 2.

2 JENIS OPERASI KITAR BACA KITAR TULIS

KITAR BACA
Cpu hantar isyarat Bas tidak sibuk
Melalui bas kawalan, jika bas dlm keadaan sibuk, CPU akan berada dlm keadaan tunggu CPU akan letakkan alamat arahan pada bas alamat

Oleh litar dalam memori atau Alamat dinyahkod/terjemah antaramuka input/output Ditempatkan pada bas data Data pada alamat yg didapati
Thava kumar A/L Devanayagam 316

BAS ALAMAT
BAS DATA BAS KAWALAN
2
MEMORI

SISTEM BAS

1
PERMINTAAN LANGKAH 1 : BACA PERMINTAAN LANGKAH 2 : KIRIM ALAMAT

RAM

ROM

MPU

BAS ALAMAT BAS DATA BAS KAWALAN


3 MEMORI RAM ROM 4

SISTEM BAS

PERMINDAHAN DATA

MPU

LANGKAH 3 : TERIMA DATA LANGKAH 4 : ISYARAT OK

KITAR BACA
Thava kumar A/L Devanayagam 317

KITAR TULIS
Boleh Isyarat Jika bas data tidak sibuk CPU menghantar data kpd memori atau alat input/output. CPU akan kirim isyarat (meminta utk menulis) pada bas kawalan Data diletakkan pada bas data, di mana lokasi alamat akan ditempatkan pada bas alamat. CPU akan kirim data ke destinasi (alamat yang telah ditetapkan)

Thava kumar A/L Devanayagam

318

Bas Alamat Bas Data Bas Kawalan


1 MEMORi RAM ROM

SISTEM BAS

MPU

PERMINTAAN
LANGKAH 1 : PERMINTAAN TULIS

Bas Alamat
3

Bas Data

SISTEM BAS

Bas kawalan
4 MEMORi

PEMINDAHAN DATA

MPU
RAM ROM

LANGKAH 2 : KIRIM ALAMAT LANGKAH 3 : KIRIM DATA LANGKAH 4 : ISYARAT OK

KITAR TULIS
Thava kumar A/L Devanayagam 319

JADUAL JULAT PETA MEMORI UTK 64K


KAPASITI (BYTES) ALAMAT (HEX)

KOMPONEN

JULAT (DECIMAL)

ROM I/O RAM Tidak diguna

12K 4K 16K 32K

0000 - 2FFF 3000 - 3FFF 4000 - 7FFF 8000 - FFFF

0 - 12287 12288 - 16383 16384 - 32767 32768 - 65535

Jumlah

64K

0000 - FFFF

0 - 65535

Thava kumar A/L Devanayagam

320

PRINSIP AMBIL DAN LAKSANA OLEH INGATAN UTAMA


Prinsip ambil dan laksana oleh ingatan utama yang berantaramuka dengan mikropemproses menggunakan bas data, alamat dan kawalan Masa perlaksanaan setiap suruhan dinamakan kitar suruhan. Kitar suruhan terdiri daripada 3 kitar: a) Kitar pungut (fetch): ambil suruhan daripada ingatan. b) Kitar Nyahkod (decode): tafsirkan suruhan yang diterima c) Kitar Laksana (execution) : laksana suruhan
Thava kumar A/L Devanayagam 321

KITAR PUNGUT

KITAR LAKSANA

Thava kumar A/L Devanayagam

322

KITAR PUNGUT
Mikropemproses mengambil satu suruhan dari ingatan dan mengisikannya ke dalam daftar suruhan (instruction register- IR). Daftar ini tidak kelihatan pada pengaturcara tetapi digunakan oleh Unit Kawalan untuk menentukan operasi yang perlu dilaksanakan.

Thava kumar A/L Devanayagam

323

KITAR NYAHKOD
Mikropemproses akan menentukan jenis suruhan yang terkandung di dalam daftar suruhan. Maklumat yang didapati dalam kitar ini diserahkan kepada kitar seterusnya.

Thava kumar A/L Devanayagam

324

KITAR LAKSANA
Mikropemroses melakukan apa yang disuruh oleh suruhan yang dipungut

Thava kumar A/L Devanayagam

325

Chapter 6
Masukan / Keluaran & Pengantaramukaan Input / Output & Interfacing

Thava kumar A/L Devanayagam

326

Masukan / Keluaran

Sebuah sistem mikropemproses melakukan berbagai tugas atau


kerja dari masa ke semasa. Sebagai contoh, menerima data dari peranti masukan, memproses data, menghantar data ke peranti keluaran. Kawalan operasi ini, khasnya didalam pemindahan data dari atau ke peranti luaran (peranti masukan/keluaran) dilakukan dengan beberapa cara atau kaedah iaitu: Perpindahan Terus (Conditional Data Transfer) Perpindahan Sampukan (Interrupt) Capaian Pengalamatan Terus (DMA) Capaian Jabat-Tangan ( Hand-Shaking )

Thava kumar A/L Devanayagam

327

1. Pemindahan terus
Peranti I/O Tidak perlu Pemindahan data Bersedia untuk menerima/memberi data Apa-apa isyarat keluaran sblm pemindahan data dilakukan Di bawah kawalan aturcara iaitu dgn bantuan arahan khusus spt IN atau OUT Mesin NC (numerical Controller) yang digunakan utk menggerudi. Masukan dalah bentuk kod berangka mudah dan keluaran adalah disambung terus ke penggerak

Contoh Penggunaan

Thava kumar A/L Devanayagam

328

2. Sampukan
Definisi sampukan Satu isyarat yang boleh dihantar pada bila-bila masa dan menyebabkan mikropemproses berhenti melakukan kerja untuk melayan isyarat sampukan tersebut. Perkakasan (hardware) yang mengizinkan peranti luar utk mendapatkan perhatian mikropemproses

Konsep

Contoh

Apabila kekunci komputer ditekan, mikropemproses akan memaksa operasi dalaman bercabang melompat ke suatu lokasi di mana terdapat satu susunan tatacara utk membaca papan kekunci tsbt.
Thava kumar A/L Devanayagam 329

Jenis sampukan

1. Maskable Interrupt Isyarat sampukan yand boleh diterima atau tidak oleh mikropemproses bergantung pada keutamaan menjalankan proses. 2. Nonmaskable Interrupt Isyarat sampukan mesti diterima oleh mikropemproses. 1. Utk memastikan alat I/O atau alat persisian menyampuk mikropemproses. 2. Utk mengurangkan masa dan kos dgn cara sampukan terjadi apabila mikropemproses menerima isyarat sampukan.

Kebaikan sampukan

Thava kumar A/L Devanayagam

330

INTERRUPTS IN 8085
Interrupt is a process where an external device can get the attention of the microprocessor.

The process starts from the I/O device The process is asynchronous.
Classification of Interrupts

Interrupts can be classified into two types:


Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected)
Thava kumar A/L Devanayagam 331

INTERRUPTS IN 8085
Interrupts can also be classified into: Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device) An interrupt is considered to be an emergency signal that may be serviced.

The Microprocessor may respond to it as soon as possible.

Thava kumar A/L Devanayagam

332

INTERRUPTS IN 8085
The 8085 has 5 interrupt inputs. The INTR input. The INTR input is the only non-vectored interrupt. INTR is mask-able using the EI/DI instruction pair.

RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. RST 5.5, RST 6.5, and RST 7.5 are all mask-able.
TRAP is the only non-mask-able interrupt in the 8085 TRAP is also automatically vectored.

Thava kumar A/L Devanayagam

333

INTERRUPTS IN 8085
Non vectored interrupts: The 8085 recognizes 8 RESTART instructions: RST0 RST7 . Each of these would send the execution to a predetermined hard-wired memory location:
Restart Instruction RST0 RST1 RST2 RST3 RST4 Equivalent to CALL 0000H CALL 0008H CALL 0010H CALL 0018H CALL 0020H

RST5
RST6 RST7

CALL 0028H
CALL 0030H CALL 0038H

Thava kumar A/L Devanayagam

334

INTERRUPT PRIORITY
Interrupt name TRAP RST 7.5 RST 6.5 RST 5.5 INTR Mask-able No Yes Yes Yes YES
Thava kumar A/L Devanayagam

Vectored Yes Yes Yes Yes NO


335

SIM INSTRUCTION ( SET INTERRUPT MASK)


7 6 5 4 3 2 1 0

SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5 RST5.5 Mask RST6.5 Mask RST7.5 Mask

Serial Out Data

0 - Available 1 - Masked

Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin

Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2

Not Used

Force RST7.5 Flip Flop to reset

SIM Instruction helps activate a particular interrupt. It can also mask a maskable interrupt.
Thava kumar A/L Devanayagam 336 336

SIM INSTRUCTION
Example: Set the interrupt masks so that RST5.5 is enabled, RST6.5 is masked, and RST7.5 is enabled. First, determine the contents of the accumulator.
- Enable 5.5 - Disable 6.5 - Enable 7.5 - Allow setting the masks - Dont reset the flip flop - Bit 5 is not used - Dont use serial data - Serial data is ignored bit 0 = 0 bit 1 = 1 bit 2 = 0 bit 3 = 1 bit 4 = 0 bit 5 = 0 bit 6 = 0 bit 7 = 0

EI MVI A, 0A SIM

; Enable interrupts including INTR ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5 ; Apply the settings RST masks

Thava kumar A/L Devanayagam

SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5


0 0 0 0 1 0 1 0

337

RIM INSTRUCTION READ INTERRUPT MASK


7 6 5 4 3 2 1 0

SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 RST5.5 Mask RST6.5 Mask RST7.5 Mask

Serial Data In RST5.5 Interrupt Pending RST6.5 Interrupt Pending RST7.5 Interrupt Pending

0 - Available 1 - Masked

Interrupt Enable Value of the Interrupt Enable Flip Flop

Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts. Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending.
Thava kumar A/L Devanayagam 338

3. Capaian Ingatan Terus


Definisi DMA Membenarkan persisian spt pemacu cakera keras (hard disk drive) memuatkan data secara terus ke dalam ingatan utama tanpa melalui mikropemproses Perlu DMAC Satu perkakasan khas yang dikenali sbg pengawal capaian ingatan terus (DMAC) Adalah satu litar bersepadu (IC) khas yang berfungsi spt 1 satu co-processor (pemproses bersama) krn ianya mampu mengambil alih kawalan sistem bas CPU.

Kebaikan DMA

i.

ii.

Pemindahan data berlaku dgn pantas krn ia tidak perlu melalui mikropemproses. Kadar pemindahan data menggunakan DMA adalah di antara 10-50 Mbyte/sesaat. Mikropemproses boleh digunakan utk menjalankan fungsi/tugas lain semasa pemindahan data secara DMA dijalankan. INi menjimatkan masa pengguna.
Thava kumar A/L Devanayagam 339

iii. Dapat menghantar byk data dlm blok yang besar iv. Pemindahan data boleh dilakukan dgn cepat dari satu blok ingatan ke blok ingatan yang lain. v. Pemindahan data boleh dilakukan dari peranti terus ke ingatan tanpa melalui mikropemproses Keburukan DMA i. Perlu perkakasan tambahan iaitu DMAC untuk memantau pemindahan data antara alat persisian dengan ingatan Kos perkakasan tinggi Prestasi CPU akan sedikit terganggu krn penggunaan sistem bas CPU

ii. iii.

Contoh DMA

Menghubungkan pemacu cakera liut( floppy disk drive) dan sistem ingatan sekunder lain dgn ingatan utama RAM. IC DMA yang biasa digunakan untuk kawalan pemacu cakera liut ialah 8271. Bg mikropemproses 68000 ialah M68450.

Thava kumar A/L Devanayagam

340

CPU chip register file ALU

I/O Bus

system bus

memory bus

bus interface

I/O bridge

main memory

I/O bus

USB controller
mouse keyboard

graphics adapter monitor

disk controller

Expansion slots for other devices such as network adapters.

disk
Thava kumar A/L Devanayagam 341

CPU chip

Reading a Disk Sector (1)


register file ALU

bus interface

CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller.
main memory

I/O bus

USB controller mouse keyboard

graphics adapter monitor

disk controller

disk
Thava kumar A/L Devanayagam 342

Reading a Disk Sector (2)


CPU chip register file ALU

Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory.

bus interface

main memory

I/O bus

USB controller
mouse keyboard

graphics adapter monitor

disk controller

disk
Thava kumar A/L Devanayagam 343

CPU chip

Reading a Disk Sector (3)


ALU

register file

When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU)

bus interface

main memory

I/O bus

USB controller
mouse keyboard

graphics adapter monitor

disk controller

disk
Thava kumar A/L Devanayagam 344

DMA

Thava kumar A/L Devanayagam

345

8257 DMA
It is a 4 Channel DMA containing 4 individual I/P ,O/P Channels. CH0,CH1,CH2,CH3 It is compatible with Intel processors. The maximum frequency is 3 MHz. It executes 3 cycles: 1. DMA read 2. DMA write. 3. DMA verify. The external device can terminate DMA Operation

Thava kumar A/L Devanayagam

346

OPERRATING MODES OF 8257


1. 2. Rotating priority mode: Each channel has equal priority.
Priority is shifted from one channel to other.

3. 4. 5.

Fixed priority mode: Each channel has a fixed priority and if higher priority channels are busy then smaller priority will get to serve. Extended write mode: This mode is used to interface slower devices to the system. TC stop mode: If this bit is set the channel whose terminal count is reached is disabled. Auto reload mode: If this bit is set data is transferred by channel 2 only. All other channels are not used.

Thava kumar A/L Devanayagam

347

4. Jabat tangan (hand shaking)


Definisi Jabat tangan Proses tak segerak (asynchronous) di mana penghantar dan penerima bertukar-tukar isyarat untuk memindahkan data. i. ii. Mikropemproses memeriksa talian bas, bersedia cari peranti persisian. Sekiranya ia rendah (tidak sibuk), mikropemproses akan menghantar isyarat strobe (STB) ke peranti persisian. Peranti persisian meletak data di output register dan bersedia bagi memindahkan data. Mikropemproses membaca data dari bas data. Talian busy/ready (busy) Mikropemproses menghantar isyarat acknowledge (ACK) ke peranti persisian bagi menghantar data seterusnya.
Thava kumar A/L Devanayagam 348

Operasi

iii. iv.

Teknik memasukkan dan mengeluarkan data dari komputer selari atau siri

Thava kumar A/L Devanayagam

349

SERIAL COMMUNICATION
Serial Communications systems are of three types: Simplex: This is a one way communication. Only one party can speak. The other party only hears to the first one but cant communicate. System A System B
Transmitter

unidirectional

Receiver

Thava kumar A/L Devanayagam

350

SERIAL COMMUNICATION
System A
Transmitter/ Receiver

System B OR
Receiver/ Transmitter

Half Duplex: It is a two way communication between two ports provided that only party can communicate at a time.

When one party stops transmitting the other starts transmitting.


The first party now acts as a receiver.
Thava kumar A/L Devanayagam 351

SERIAL COMMUNICATION
Transmitter/ Receiver Receiver/ Transmitter.

OR/AND.

Full Duplex: It is a two way communication between two ports and both parties can communicate at same time. Thus here efficient communication can be established.

Thava kumar A/L Devanayagam

352

CIRI-CIRI PENGHANTARAN SELARI


Setiap bit Perpindahan data Data mempunyai talian berasingan dan kesemua bit dihantar secara serentak. Segerak iaitu sama ada dalam bentuk byte, word atau longword.

Perhantaran data
Kabel

Lebih cepat

Perlu kabel banyak, maka kos tinggi, oleh itu, hanya sesuai untuk jarak dekat < 100 kaki, contoh: sambungan antara komputer ke printer, monitor atau keyboard.

Kaedah peng. selari

Digunakan bagi penghantaran data di dalam komputer iaitu di antara: CPU ke peranti I/O secara terus

Thava kumar A/L Devanayagam

353

Keburukan

1.
2.

3.

Kos yang tinggi disebabkan banyak wayar dan daftar-daftar Terjana noise (gangguan) jika penghantaran selari digunakan di antara komputer dengan peranti persisian. Sukar mengesan talian yang rosak

Thava kumar A/L Devanayagam

354

CIRI-CIRI PENGHANTARAN SIRI


Setiap bit Perhantaran data Kabel Data binari akan dihantar satu persatu melalui satu talian iaitu satu bit setiap masa Adalah lambat Perlu satu kabel banyak, maka kos murah, oleh itu, hanya sesuai untuk jarak jauh < 100 kaki, contoh:mikrokomputer perlu disambung kepada peranti persisian melalui talian telifon. Digunakan bagi penghantaran data di dalam komputer iaitu di antara: 1. CPU dan memory 2. CPU dan I/O devices 3. Memory dan I/O devices 1. mudah mengesan talian yang rosak
Thava kumar A/L Devanayagam 355

Kaedah peng. siri

Keburukan

PENGHANTARAN SIRI
Teknik terbahagi 2: i. Teknik tak segerak ii. Teknik segerak Terdapat kod mula dan henti Penghantaran blok dalam satu masa

Thava kumar A/L Devanayagam

356

PENGHANTARAN SIRI TAK SEGERAK

apabila menggunakan satu bit mula untuk penerima mengenal pasti permulaan aksara dan 1 atau 2 bit berhenti untuk tanda akhiran aksara

Thava kumar A/L Devanayagam

357

PENGHANTARAN SIRI SEGERAK

Apabila berhubung secara segerak alat penerima dan penghantaran disegerakkan oleh clock yang sama fasa dan kelajuannya. Data akan dihantar dalam bentuk blok. Penghantaran data segerak digunakan untuk penghantaran berhalaju tinggi, tanpa lengahan antara setiap elemen aksara.
Thava kumar A/L Devanayagam 358

TRANSMISSION FORMATS
Asynchronous 1. Synchronous It transfers group of characters at a time.

It transfers one character at a 1. time.

2. Used for transfer data rates <20KBPS 3. Start and stop bit for each character which forms a frame.

2. Used for transfer data rates >20KBPS 3. No start and stop bit for each character.

4. Two Clocks are used for Tx and Rx

4. Single clock is used for both Tx and Rx.


359

Thava kumar A/L Devanayagam

PERANTARAMUKA
Definisi perantaramuka Mengawal pergerakan data antara komputer dan peranti persisian (peripherals devices) seperti keyboard, printer, switches, display lamps dan plotter 1. 2. 3. PIA (Programmable Interface Adapter) PPI (Programmable Peripheral interface) PIT ( Parallel Interface Timer) UART (Universal asynchronous receiver/transmitter) ACIA (Asynchronous Communication Interface Adapter)

Contoh Perantaramuka Selari

Contoh Perantaramuka Siri 1. 2.

Thava kumar A/L Devanayagam

360

Fungsi UART

Menukarkan data selari yang dihasilkan oleh CPU pertama ke bentuk bersiri yang kemudiannya dihantar ke peranti penerima. Data bersiri ini perlu ditukar semula ke selari sebelum dihantar ke CPU kedua 1. Daftar anjakan, menukarkan data selari ke siri dan sebaliknya.

Komponen utama UART Rajah

Thava kumar A/L Devanayagam

361

Fungsi ACIA

Pengkalan data siri di mana ia berfungsi sebagai perantaramuka di antara data siri dan selari 1. 2. Data masuk adalah siri Data disimpan di dlm daftara data sebelum dihantar serentak secara selari.
Data series input 7 6 5 4 3 2 1 0

Ciri-ciri ACIA

Data 0 7 parallel output

Contoh

1.

Isyarat dari peranti persisian adalah siri. Oleh krn pergerakan data dalam sistem mikropemproses adalah selari maka isyarat yang masuk ini perlulah ditukar ke bentuk selari sebelum diproses oleh CPU

Thava kumar A/L Devanayagam

362

Fungsi kabel RS232

Kabel penyambungan data bersiri yang digunakan secara meluas bagi menyambungkan peranti persisian dengan komputer. 1. 2. 3. Mempunyai 20 talian Biasanya hanya sedikit daripada talian-talian ini digunakan Menghubungkan peralatan pengkalan data (DTE Data terminal equipment) dengan peralatan penamatan litar data (DCE Data Communication Equipment). DCE ialah computer , DTE biasanya modem

Ciri-ciri ACIA

Contoh Rajah

1.

Thava kumar A/L Devanayagam

363

8085 Memory Interfacing


Generally P 8085 can address 64 kB of memory .

Generally EPROMS are used as program memory and RAM as data memory.
We can interface Multiple RAMs and EPROMS to single P .

Memory interfacing includes 3 steps :


1.Select the chip. 2.Identify register. 3.Enable appropriate buffer.
Thava kumar A/L Devanayagam 364

8085 Memory Interfacing


Example: Interface 2Kbytes of Memory to 8085 with starting address 8000H. Initially we realize that 2K memory requires 11 address lines (2^11=2048). So we use A0-A10 . Write down A15 A0

A15
1

14 0

13 0

12 0

11 0

10 0

9 0

8 0

7 0

6 0

5 0

4 0

3 0

2 0

1 0

0 0

ADD 8000H

87FFH

Thava kumar A/L Devanayagam

365

8085 Memory Interfacing


Address lines A0-A10 are used to interface memory while A11,A12,A13,A14,A15 are given to 3:8 Decoder to provide an output signal used to select the memory chip CSor Chip select input. MEMR and MEMWare given to RDand WRpins of Memory chip. Data lines D0-D7 are given to D0-D7 pins of the memory chip. In this way memory interfacing can be achieved.

Thava kumar A/L Devanayagam

366

8085 Memory Interfacing


The diagram of 2k interfacing is shown below:
A15- A11
3:8DECODER

8085
A15-A8
ALE
CS

A10- A0
AD7-AD0 Latch

A7- A0

2K Byte Memory Chip

WR RD

IO/M

D7- D0
RD WR

Thava kumar A/L Devanayagam

367

8085 Memory Interfacing


In this example we saw that some address lines are used for interfacing while others are for decoding.

It is called absolute decoding.


We sometimes dont requires that many address lines.So we ignore them.But this may lead to shadowing or multiple address. This type of decoding is called linear decoding or partial decoding.

In partial decoding wastage of address takes place but it requires less hardware and cost is also less as compared with absolute one.
Thava kumar A/L Devanayagam 368

8255 PIN DIAGRAM


PA0-PA7 PB0-PB7 PC0-PC7 D0-D7 RESET RD I/O I/O I/O I/O I I Port A Pins Port B Pins Port C Pins Data Pins Reset pin Read input

WR
A0-A1 CS Vcc , Gnd

I
I I I

Write input
Address pins Chip select +5volt supply
Thava kumar A/L Devanayagam 369

8255 BLOCK DIAGRAM

Thava kumar A/L Devanayagam

370

8255 BLOCK DIAGRAM


Data Bus Buffer: It is an 8 bit data buffer used to interface 8255 with 8085. It is connected to D0-D7 bits of 8255. Read/write control logic:It consists of inputs RD,WR,A0,A1,CS . RD,WR are used for reading and writing on to 8255 and are connected to MEMR,MEMW of 8085 respectively. A0,A1 are Port select signals used to select the particular port . CS is used to select the 8255 device . It is controlled by the output of the 3:8 decoder used to decode the address lines of 8085.

Thava kumar A/L Devanayagam

371

8255 BLOCK DIAGRAM


A0,A1 decide the port to be used in 8255.
A1 A0 Selected port Port A

0
1 1

1
0 1

Port B
Port C Control Register

Thava kumar A/L Devanayagam

372

8255 BLOCK DIAGRAM


1. 2. Group A and Group B Control: Group A control consists of Port A and Port C upper. Group B control consists of Port A and Port C lower. Each group is controlled through software. They receive commands from the RD, WR pins to allow access to bit pattern of 8085. The bit pattern consists of : Information about which group is operated. Information about mode of Operation.

Thava kumar A/L Devanayagam

373

8255 BLOCK DIAGRAM


PORT A,B:These are bi-directional 8 bit ports each and are used to interface 8255 with CPU or peripherals. Port A is controlled by Group A while Port B is controlled by Group B Control. PORT C: This is a bi-directional 8 bit port controlled partially by Group A control and partially by Group B control . It is divided into two parts Port C upper and Port C lower each of a nibble. It is used mainly for control signals and interfacing with peripherals.
Thava kumar A/L Devanayagam 374

8255 MODES
Mode 0 : Simple I/O Any of A, B, CL and CH can be programmed as input or output Mode 1: I/O with Handshake A and B can be used for I/O C provides the handshake signals Mode 2: Bi-directional with handshake A is bi-directional with C providing handshake signals B is simple I/O (mode-0) or handshake I/O (mode-1) BSR (Bit Set Reset) Mode Only C is available for bit mode access. Allows single bit manipulation for control applications

Thava kumar A/L Devanayagam

375

INTERFACING 8085 & 8255


Here 8255 is interfaced in Memory Mapped I/O mode. Initially we write down the addresses and then interface it .
A15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port

CW

Thava kumar A/L Devanayagam

376

INTERFACING 8085 & 8255


Thus we get addresses ,considering dont cares to be zero as
Port A =8000H Port B =8001H Port C =8002H CWR =8003H

Then,we give A11,A12,A13 pins to A,B,C inputs of Decoder to enable 8255 or Chip Select. A15 is logic 1 so it is given to active HIGH G1 pin& A14 ,IO/M are given to active low G2B ,G2A pins. Output from Latch is given as A0,A1 pins to 8255 while D0D7 are given as data inputs.
Thava kumar A/L Devanayagam 377

INTERFACING 8085 & 8255


A15 A14 IO/M G2A G2B G1

A13 A12 A11

A B C

PA
/CS

8085
ALE
(AD0-AD7)

3:8 decoder

8255 PB

O0 74373O1
A0-A7

A0 A1

O7 D7-D0

PC

RD WR

RD WR

Thava kumar A/L Devanayagam

378

INTERFACING 8085 & 8255


Example:Take data from 8255 port B.Add FF H .Output result to port A. MVI A,82H Initialize 8255. OUT 83H LDA 81H Take data from port B ADI FFH Add FF H to data OUT 80H. OUT Result to port A. RST1. STOP.

Thava kumar A/L Devanayagam

379

INTERFACING STEPPER MOTOR with 8255

Thava kumar A/L Devanayagam

380

8253 PIT

Thava kumar A/L Devanayagam

381

8253 Features
Three independent 16 bit counters. 24 pin Dual in line Package. Counting facility in Both BCD and Binary modes. Dc to 2 MHz operating Frequency. Can be used as a clock generator.

Thava kumar A/L Devanayagam

382

CONTROL WORD
D7 D0

SC1 SC0 RL1 RL0 M2


SC1 SC0 Select counter RL1

M1

M0
RL0

BCD
Read/Load

0
0 1 1

0
1 0 1

Counter0
Counter1 Counter2

0 0
1

0 1
0

Counter latching Read/load LSB


Read/load MSB

ILLEGAL 1
Thava kumar A/L Devanayagam

R/L MSB 1st then LSB.


383

CONTROL WORD
M2
0 0 X X 1

M1
0 0 1 1 0

M0
0 1 0 1 0 Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 BCD =0 Binary counter BCD =1 BCD counter

Mode 5

Thava kumar A/L Devanayagam

384

8253 SQUARE WAVE


Example: Use 8253 as a square wave generator with 1ms period if the input frequency is 1MHz. We use counter 0 as a square wave generator and address of counter 0 =10H and control register =13H. I/P frequency is 1MHz.So time is 1sec. Count value = Required period /Input period = 1ms/1 sec =1000(Decimal). Thus we use 8253 as a decimal counter.

Thava kumar A/L Devanayagam

385

8253 SQUARE WAVE


Program: MVI A,37H Initialize counter 0 mode 3 OUT 13H 16 bit count BCD MVI A,00H Load LSB count to counter 0 OUT 10H MVI A,10H Load MSB count to counter 0 OUT 10H. Thus, the output will be a square wave.

Thava kumar A/L Devanayagam

386

MIKROPEMPROSES 16 BIT DAN 32 BIT

Thava kumar A/L Devanayagam

387

MICPROCESSOR 8 BIT (Intel 8085) I byte CPU and ALU architecture are those that are based on registers, address buses, or data buses of data size 8 bit data bus

MICPROCESSOR 16 BIT (Intel 8086) 2 byte CPU and ALU architecture are those that are based on registers, address buses, or data buses of data size 16 bit data bus

Thava kumar A/L Devanayagam

388

Você também pode gostar