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Introduction
Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): millions of logic gates + many Mbits of memroy Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
A Brief History
1958: First integrated circuit
Built by Jack Kilby at Texas Instruments with 2 transistors
2003
Intel Pentium 4 mprocessor (55 million transistors) 512 Mbit DRAM (> 0.5 billion transistors) No other technology has grown so fast so long
Annual Sales
1018 transistors manufactured in 2003 100 million for every human on the planet $100B business in 2004
Global Semiconductor Billings (Billions of US$)
200
150
100
50
0 1982
1984
1986
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1996
1998
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Year
Transistor Types
Bipolar transistors
npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density (power dissipation issue)
nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration (ideally zero static power)
Moores Law
1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 18 months
1,000,000,000
Integration Levels
Pentium 4 Pentium III Pentium II Pentium Pro Pentium
100,000,000
10,000,000
SSI:
MSI: LSI: VLSI:
10 gates
1000 gates 10,000 gates > 10k gates
Transistors
1,000,000 Intel386 100,000 8086 10,000 8008 4004 1,000 8080 80286
Intel486
1970
1975
1980
1985
1990
1995
2000
Year
Corollaries
Many other factors grow exponentially Ex: clock frequency, processor performance
10,000 1,000 4004 8008 8080 100 8086 80286 Intel386 10 Intel486 Pentium Pentium Pro/II/III 1 Pentium 4
1970
1975
1980
1985
1990
1995
2000
2005
Year
Silicon Lattice
Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si Si Si Si Si Si Si Si Si
Dopants
Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic): extra electron (n-type) Group III (Boron): missing electron, called hole (p-type)
Si Si Si Si Si Si Si Si Si Si Si B Si Si Si
+ -
As Si
Si
p-n Junctions
A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction
p-type anode
n-type cathode
nMOS Transistor
Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor
Source Gate Drain Polysilicon SiO2
n+ p
n+ bulk Si
nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2
0
n+ p
n+
S D
bulk Si
n+ p
n+
S D
bulk Si
0: Introduction
Slide 15
pMOS Transistor
Similar, but doping and voltages reversed Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO2 Gate Drain
p+ n
p+ bulk Si
Transistors as Switches
We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain
g=0 d nMOS g s s d ON s s s d OFF s d OFF g=1 d ON
d pMOS g
CMOS Inverter
A
0 1
VDD A Y
GND
CMOS Inverter
A
0 1 0
VDD OFF
A=1 Y=0
ON
A Y
GND
CMOS Inverter
A
0 1
Y
1 0
VDD ON
A=0 Y=1
OFF
A Y
GND
Y A B
1
1
0
1
ON A=0 B=0
1
1
0
1
ON Y=1 OFF ON
1
1
0
1
0: Introduction
Slide 24
ON A=1 B=0
1
1
0
1
A B Y
1
1
0
1
0
0
Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network pMOS pull-up network a.k.a. static CMOS
Pull-up OFF Pull-down OFF Z (float) Pull-down ON 0 Pull-up ON 1 X (crowbar)
pMOS pull-up network
inputs output
nMOS pull-down network
a g1 g2
(b)
a g1 b (c) g2 0
a 0 b OFF 0
a 1 b ON 1
a 0 b ON 1
a 1 b ON
a g1 b (d) g2 0
a 0 b ON 0
a 1 b ON 1
a 0 b ON 1
a 1 b OFF
Conduction Complement
Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS A Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel
B
Compound Gates
Compound gates can do any inverting function Ex: Y A B C D (AND-AND-OR-INVERT, AOI22)
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D
A (c) C A
B C
Example: O3AI
Y A B C D
Example: O3AI
Y A B C D
A B C D Y D A B C
Well
Requires to build both pMOS and nMOS on single wafer. To accommodate both pMOS and nMOS devices, special regions must be created in which the semiconductor type is oppossite of the substrate type. Also Known as Tubs.
Twin-tubs
Flow Diagram
Create n-Well regions and Channel Stops region Grow Field Oxide and Gate Oxide Deposite and pattern Polysilcon Layer Implant sources, drain regions and substrate contacts
Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1
p+
n+
n+ p substrate
p+ n well
p+
n+
substrate tap
well tap
VDD
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
Pattern Preparation
Chrome Pattern
Pellicle
Quartz Substrate
Wafer Preparation
Wafer Preparation
Fabrication Steps
Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate
Oxidation
Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
Photolithography
Exposure Processes
Photoresist
Used for lithography . Lithography is a process used to transfer a pattern to layer on the chip. Similar to Printng Process Spin on photoresist (about 1 mm thickness) Photoresist is a light-sensitive organic polymer Possitive Photoresist: Softens where exposed to light Negative Photresist: Harden where exposed to light, Not used in practise generally
Photoresist SiO2
p substrate
Lithography
Expose photoresist through n-well mask Strip off exposed photoresist
Photoresist SiO2
p substrate
Etch
Cluster Tool Configuration Wafers Etch Chambers Transfer Chamber Loadlock
RIE Chamber
Exhaust
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Photoresist SiO2
p substrate
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
SiO2
p substrate
n-well
n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well
Ion Implantation
Focus Beam trap and gate plate Neutral beam and beam path gated
Y - axis scanner
X - axis scanner
Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
n well p substrate
Polysilicon
Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Polysilicon Thin gate oxide n well p substrate
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact
n well p substrate
N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing
n+ Diffusion
n well p substrate
N-diffusion cont.
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n+
n+ n well p substrate
n+
N-diffusion cont.
Strip off oxide to complete patterning step
n+
n+ n well p substrate
n+
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+ p substrate
p+ n well
p+
n+
Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
Contact
Metalization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
Metal
Testing
Defective IC
Individual integrated circuits are tested to distinguish good die from bad ones.
gold wire
bonding pad
connecting pin
Final Test
Chips are electrically tested under varying environmental conditions.
Based on the Principal of selectively Growing the oxide rahter than etching. Selectice Growth is achieved by shielding the Active area with Silicon Nitride (Si3N4) First Thin oxide is grown followed by deposition and patterning of Silicon Nitride (Si3N4)
Exposed area form the isolation region and doped with P Kind of impurities
Thick oxide is grown in next step where the area is not covered by Si3N4.
Etching of Si3N4 and thin Oxide. Most Popular Techniques. Later Some techniques are developed to control Birds Beak Region.
Summary
MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!
References
1. 2. 3. 4. 5. 6. 7. 8. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997. Semiconductor Processing with MKS Instruments, Inc. Worthington, Eric. New CMP architecture addresses key process issues, Solid State Technology, January 1996. Leskonic, Sharon. Overview of CMP Processing, SEMATECH Presentation, 1996. Gwozdz, Peter. Semiconductor Processing Technology SEMI, 1997. CVD Tungsten, Novellus Sales Brochure, 7/96. Fullman Company website. Fullman Company - The Semiconductor Manufacturing Process, http://www.fullman.com/semiconductors/index.html, 1997. Barrett, Craig R. From Sand to Silicon: Manufacturing an Integrated Circuit, Scientific American Special Issue: The Solid State Century, January 22, 1998.
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