Escolar Documentos
Profissional Documentos
Cultura Documentos
Chapter 1
Intel Hub Architecture block diagram Intel Hub Link Bus attributes
Explain
Explain
Describe
M-1
Processor
System Memory
Clock Gen
HubLink Bus
CNR
SM Bus
South Bridge (ICH)
The Chipset consists of the North Bridge, South Bridge and Firmware Hub
LPC Bus
Mouse
FWH
SIO
Intel PC Chipsets
Include Various
Support
Chipset Components
The
Supports either: (depends on version) Direct AGP - fully integrated graphics engine - no external AGP slot - used for Value PC or AGP 2.0 (with AGP slot) Support for analog video, Digital Video Out (DVO) and Display Data Channel (DDC)
PC Chipset: Bus Architecture CH-1 Slide-5
M-1
4: FWH
CH-1 Slide-6
Chipset Components
The
The
Stores BIOS code/data in 512KB or 1MB flash memory Random number generator Can be reprogrammed in place
CH-1 Slide-7
Proprietary
ICH
Eight
66.6MHz clock signal derived from AGP clock May also be 16 bit data and/or 100MHz clock
Data
can be transferred at 4 bytes per clock cycle design and operation is Intel proprietary
Hublink
CH-1 Slide-8
Each
contain PCI devices which are designated with a one byte ID--the MCH contains 2 devices; GMCH has 3.
Host bus to PCI bus 0 interfaces with system memory controller to AGP bus to extend outside the MCH
When
video out
Display
PC Chipset: Bus Architecture
Host Bus
BUS 0 DEVICE 0
Host-Hub Bridge B0:D0:F0
BUS 2 DEVICE 0
AGP Slot B2:D0:F0
BUS 0 DEVICE 1
PCI-AGP Bridge B0:D1:F0
SCS[11:1]# SMA[12:1] SBS[1:0] SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] RDCLK0 RDCLKIN
Hub Interface
HL [11:0]
HL_STB
CH-1 Slide-10
Host Bus
BUS 0 DEVICE 0
Host-Hub Bridge B0:D0:F0
BUS 2 DEVICE 0
AGP Slot B2:D0:F0
BUS 0 DEVICE 1
PCI-AGP Bridge B0:D1:F0
SCS[11:1]# SMA[12:1] SBS[1:0] SRAS# SCAS# SWE# SDQ[63:0] SCB[7:0] RDCLK0 RDCLKIN
BUS 0 DEVICE 2
Graphics Accelerator B0:D2:F0
Hub Interface
HL [11:0]
HL_STB
CH-1 Slide-11
The
ICH and MCH each contain PCI devices which are designated with a 1 byte hex number--the ICH has three:
to LPC Bridge for interface to firmware hub and Super I/O controller controller
SMB
Two
USB controllers
Audio Controller Modem Controller 10/100 Mbit/sec Ethernet and 1Mbit/sec Home PNA
CH-1 Slide-12
AC97 AC97
PCI Bus 1
Hub Interface
BUS 0 DEVICE 1E
HUB-PCI Bridge B0:D1E:F0
PCI-LPC Bridge B0:D1F:F0 USB Ctr. 1 B0:D1F:F2 IDE Controller B0:D1F:F1 USB Ctr. 2 B0:D1F:F4 SMB Controller B0:D1F:F3
BUS 1 DEVICE 8
LAN Cntr. B1:D8:F0
LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] USBP0[P:N] USBP1[P:N] OC[1:0]# USBP2[P:N] USBP3[P:N] OC[3:2]# SMBDATA SMBCLK AC_RST# AC_SYNC AC_BIT_CLK AC_SDOUT AC_SDIN0 AC_SDIN1
CH-1 Slide-13
DEVICE 1F
data books use DECIMAL numbers to identify devices: e.g., Device 1Eh = 30(10) ; Device 1Fh = 31(10)
PCI Bus 1
Hub Interface
BUS 0 DEVICE 1E
HUB-PCI Bridge B0:D1E:F0
BUS 1 DEVICE 8
LAN Cntr.
B1:D8:F0
0 : 30 : 0 0 : 31 : 0 0 : 31 : 1 0 : 31 : 2 0 : 31 : 3
0 : 31 : 4
Audio Ctr. B0:D1F:F5
USB Ctlr 2
Audio Ctlr Modem Ctlr LAN Ctlr
CH-1 Slide-14
0 : 31 : 5
AC97 Controller
DEVICE 1F
Modem Ctr B0:D1F:F6
0 : 31 : 6 1: 8: 0
M-1
CH-1 Slide-15
The
FWH contains
into 64KB lockable blocks
Typical use of FGPI pins are to gather misc. data such as jumper settings (BIOS recovery jumper)
RNG
FWH Interface
Device shown as used in FWH Mode See chapter 3 for details on AAMux Mode
PC Chipset: Bus Architecture CH-1 Slide-17
The CNR provides the PC Industry the opportunity to deliver a flexible and cost reduced method to implement subsystems widely used in "connected PCs".
The CNR Specification is an open industry specification and is supported by OEMs, IHV card manufacturers, silicon suppliers and Microsoft. CNR Spec. calls for cards to be PnP: an EEPROM on the CNR card contains configuration information.
Upper three SMB Address bits of CNR card determined by pull up resistors on the system board.
CH-1 Slide-18
+5v
M-3
ICH
BUS 0 DEVICE 1F
USB Ctr. 2 B0:D1F:F4
OC
EE_DIN EE_DOUT EE_CS LAN_CLK LAN_RXD[2:0] LAN_TXD[2:0] * USB1[P:N] * OC# SMBDATA SMBCLK
BUS 1 DEVICE 8
LAN Cntr. B1:D8:F0
AC_RST#
CNR Connector
* USB lines may alternatively be routed from USB Host Controller ASIC
A1
CH-1 Slide-20
Chapter 1 Quiz
1) The FWH is accessed via the:
A) LPC Bus B) PCI Bus Highway Bus C) Hublink Bus D) Beaverton-Hillsdale
M-4
3) The Intel Hublink Bus can transfer data at 3.2GB/s (True / False) 4) Which of the following devices is routed to the CNR connector?
A) IDE controllerC) AGP controller B) Floppy controller D) Audio Controller
PC Chipset: Bus Architecture CH-1 Slide-21
Hub Architecture
(GMCH in value PC applications)
Contains:
MCH ICH FWH
Intel
Can transfer data between the MCH and ICH at 266MB/s Intel Proprietary
CH-1 Slide-22
contains:
PCI bus 0 to PCI bus1 to extend outside the ICH
PCI to LPC Bridge for interface to firmware hub and Super I/O IDE controller SMB controller Two USB controllers AC97 Audio Controller AC97 Modem Controller
Hub
Contains BIOS
Utilizes Flash ROM technology
Can
Communications
controller
controller
controller Controller
End of Chapter 1
CH-1 Slide-24