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VLSI Technology
Introduction (Lecture 1)
History of VLSI MOS Transistor - Introduction Transistor scaling and Moores law - BKD
Complexities involved and key design issues VLSI Design flow (analog, digital, RF, CPLD, FPGA) Role of design engineer in IC industry Manufacturing trends & ITRS Roadmap
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Introduction to VLSI
(Lecture 1) Sources:
International Technology Roadmap For Semiconductors http://public.itrs.net/ INTELhttp://www.intel.com/technology/ silicon/index.htm
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Low Complexity
VACUUM TUBES
1930-
1995-
NANO STRUCTURES
2010-
Cost
1950s
Low
First Computer
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First Transistor
Point Contact Germanium Transistor
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Shockley, Brattain & Bardeen - Bell Labs, 1948 Nobel Prize - 1956
Planar Process
p-n Junction Formation Light Mask n-Si
p-Si
oxidise Lithography b e Bipolar transistor
ox
+ p n n
Etch c
n+ n
P-Diffuse
p+
n+ p-Si
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IC Processor
INTEL Pentium IV
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IC Processor
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IC SRAM Chip
0.57 m2 cell size >0.5 billion transistors 110 mm2 chip size Fully functional 70 Mbit SRAM chips have been fabricated.
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Integrated Circuits
SSI Small Scale Integrated Circuits
Less than 10 gates e.g., 7404 inverter
MOS Structure
Gate charge
+
oxide
p-silicon
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In a metal-oxide-silicon structure, a depletion layer forms below the metal gate. For p-type silicon substrate, a positive charge develops on metal side and depletion layer is negatively charged.
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MOS Structure
M
Accumulation, VGB <VFB Flat Band, VGB =VFB VGB =0
+ + + +
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p-Si
++ ++
+ + + + + + + + +
MOS Transistor
VG Source VS
n+
Gate
VD
n+ poly-Si oxide
Drain
n+
Wdep p- Si
depletion region
n-channel
L channel length
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NMOS Transistor
NMOS Transistor
VGS > VT : Pinch-off VDS = VGSVT
Inversion-layer is pinched-off at the drain end
Electrons are swept into the drain by the E-field when they enter the pinch-off region and saturation occurs.
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MOS Transistor
6 5 4 3 2 1
X 10-4
ID 0
cutoff
0.5
1.5
2.5
VDS (V)
ID
V W n C ox ( VGS DS VT )VDS L 2
ID
W n C ox ( VGS VT ) 2 2L
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NMOS Transistor
G S gate oxide insulator
n n
Without a gate voltage applied, no current can flow between the source and drain regions. Above a certain gate-to-source voltage (threshold voltage VT), a conducting layer of mobile electrons is formed at the Si surface beneath the oxide. These electrons can carry current between the source and drain.
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PMOS
p+ poly-Si n+ p+
+++++
p+
p-type Si
n-type Si
For current to flow, VGS < VT Enhancement mode: VT < 0 Depletion mode: VT > 0
Transistor is ON when VG=0V
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PMOS Transistor
As compared to an n-channel MOSFET, the signs of all the voltages and the currents are reversed:
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MOS Structure
Gate (contact not shown) Source Drain
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MOS Structure
Transistor for 90nm process In Production
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Transistor Scaling
Scale of Things
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Intel386 DX Processor
Intel486 DX Processor
Pentium Processor
Moores Law
In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time). Amazingly visionary million transistor/chip barrier was crossed in the 1980s.
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2300 transistors, 1 MHz clock (Intel 4004) - 1971 16 Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) - 2001 140 Million transistor (HP PA-8500)
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Moores Law
Transistors on lead microprocessors double every 2 years
1000 100 Transistors (MT) 10 1 0.1 0.01 8085 8086 8080 8008 4004 1980 1990 Year 2000 2010
Courtesy, Intel
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P6 Pentium proc
0.001
1970
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Moores Law
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90 nm Montecito processor breaks through billion transistor mark ahead of trend line with 1.72B transistors
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Moores Law
100000000
4X growth every 3
10000000
Kbit capacity/chip
1000000
book
64,000,000 0.07 m years! human memory 16,000,000 0.1 m human DNA 4,000,000 0.13 m 1,000,000 0.18-0.25 m
100000
10000
1,000 1.6-2.4 m
4,000 1.0-1.2 m
16,000 0.7-0.8 m
page
DRAM Chip
1989 1992 1995 1998 2001 2004 2007 2010
1983
1986
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Year
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Moores Law
Processor power will keep doubling every two years.
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Moores Law
Transistor physical gate length will reach ~15 nm before end of this decade, and ~10 nm early next decade.
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Moores Law
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Moores Law
Moores Law
Die size grows by 14% to satisfy Moores Law
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Die Size
Die size (mm)
P6 486 Pentium proc
386
8008 4004
1 1970
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1980
1990 Year
2000
2010
Courtesy, Intel
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Moores Law
Lead microprocessors frequency doubles every 2 years
10000 1000 Frequency (Mhz) 100 486 10 1 0.1 1970
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2X every 2 years
P6 Pentium proc 8085 8086 286 8080 8008 4004 1980 1990 Year 2000
Courtesy, Intel
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386
Clock Frequency
2010
Moores Law
Lead Microprocessors power continues to increase
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Power Dissipation
Power (Watts)
10
8086 286 1
8008 4004
8085 8080
1985
1992
2000
Courtesy, Intel
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Moores Law
10000
1000
Power Density
100
Hot Plate 10 4004 P6 8008 8085 Pentium proc 386 286 486 8080 1
1970 1980 1990 Year 2000 2010
Courtesy, Intel
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Moores Law
1.E+01
Cost US$/transistor
1.E-01
1.E-03
Moores Law means Decreasing Costs: Packing more transistors into less space has dramatically reduced their cost and the cost of the products they populate.
1.E-05
1.E-07
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92
96
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04
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Year
Moores Law
Roadmap for VLSI Technology
Lithography Node (nm)
Process Ist Year of Production Gate Length (nm) Wafer (mm)
250
P856 1997 200 200
180
P858 1999 130 200
130
Px60 2001 <70 200/ 300
90
P1262 2003 <50 300
65
P1264 2005 <35 300
45
P1266 2007 <25 300
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Source ITRS
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Moores Law
Transistor for 90nm process In Production
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Moores Law
Moores Law
130 nm node 90 nm node 65 nm node 70 nm length Production-2001 50 nm length Production-2003
45 nm node
Silicon Nanowires Source: Morales & Lieber, Science 279, 280 (1998)
MEMS-based RF Switches
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Design Levels
SYSTEM
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IC Manufacture Trend
Source ITRS
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