12/4/2002

Behavioral Buffer Modeling

with HSPICE Intel Buffer
10-08-03
2
12/4/2002 Introduction
Objective
Demonstrate alternative HSPICE
behavioral simulation methods.
Can be used when the present features
of IBIS models are insufficient.
Can be used for pre-silicon feature
design characterization in a system
environment.
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12/4/2002 Introduction
Topics
Behavioral Driver models
Close gap between technology and IBIS
Convergence Advisory
Circuits with that use switches and G
elements tend to be more susceptive
to convergence problems.
High speed differential behavioral
buffer and input characterization is
an extension of these methods
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12/4/2002 Introduction
Simple CMOS Model
Rn
Rp
Cn
Components:
Complementary
Pulse source
Switch
Resistor
Capacitor
DC source
Ground
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12/4/2002 Introduction
Assignment - 1
Create simple CMOS model
Use Pspice
Rp=10 ohm, Rn=10 ohms
Adjust Cn to get a 1 ns risetime (20%
to 80%) with a 50 ohm load and 1pf tied
to ground
Hint: Use a 100MHz, 50% duty cycle for
the pulse source.
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12/4/2002 Introduction
Behavioral Model Test Program
Start with testckt file from pervious class
MYBUFF will be our new generator
DATAS will modified for different rise and
fall times.
Printed Wiring
Board
Buffers
p
a
c
k
a
g
e

p
a
c
k
a
g
e

Receiver
D
a
t
a

g
e
n
e
r
a
t
o
r

MYBUF
DATAS
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12/4/2002 Introduction
Level 1 Behavioral Model
Control
PWL VCCS
Vss
Control
PWL VCCS
Vdd
0 V 0 O
1 V O
0 V 0 O
1 V O
Buffer Pad
1.0 V
1.0 V
Profile
conditioner

Profile
conditioner

01001100
PWL source
Math Process to
create edges
in
in balancen
out
V
V R
R

=
1
* ) (
in
in balancep
out
V
V R
R

=
1
* ) (
MYBUF
DATAS
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12/4/2002 Introduction
Data pattern generator
Syntax:
changed to
yield
different bit
waveforms
with
different
rise and fall
times.
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12/4/2002 Introduction
Bit data waveform
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12/4/2002 Introduction
Creating a simple equation based V-T wave
The bit pattern is used to create a
representative PWL data wave.
A proportional unity driving waveform (v-t
wave) is created out of the PWL pulse.
The edge of the ramp of the PWL pulse is
proportional to the time for the bit transition.
The entire transition of the pulse is related to
the rise/fall time of the wave.
1.0 V
01001100
pulse(t)
wave t ( ) 1 e
pulse t ( ) ( )
wf
2.4

1.1 :=
bits
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12/4/2002 Introduction
Syntax HSPICE for driver
The circuit is completed with the voltage profile derived from
the unity driving waveform which controls a dependant
resistor tied to the n and p loads. In this case the loads are 50
ohms. We need to insure we dont divide by zero and also do
not result in an exact 0 ohm resistance.
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12/4/2002 Introduction
Convert the n & p resistors to I/V devices
The next task is to create I/V subciruits: IVN and IVP
To do this we use voltage controlled current source
(VCCS)
The G element is a piecewise linear (PWL) VCCS
To create a I/V device, the control nodes and the output
nodes are shorted
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12/4/2002 Introduction
I/V subcircuit example
The columns are
voltage on the left
and current on the
right
This forms a table
based I/V device
since the control
voltage imposed and
current are across
the same nodes
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12/4/2002 Introduction
If rising and falling edge shape
differs, another method is required
If the bit pattern is not known a priori,
controlling positive and negative shapes
independently is difficult.
In the previous example we controlled only slew
rates not shapes.
Will describe how to do this for the 2
nd
order
buffer
We will use the pulse source created as
homework for the first HSPICE class.
The edge for the pulse, if scaled correctly, can
be made equal to the time of the bit transition.
This is an important concept
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12/4/2002 Introduction
Level 2 Behavioral Model Block Diagram
Control
PWL VCCS
I-V
Vss
Control
PWL VCCS
I-V
Vdd
Control
PWL VCCS
I-V
0 V 0 O
1 V O
0 V 0 O
1 V O
Control
PWL VCCS
I-V
Buffer Pad
Write
enable
Dynamic
Clamp
Dynamic
Clamp
Bit
Pattern
P Voltage
Profile
Generator
1.0 V
N Voltage
Profile
Generator
1.0 V
Profile
conditioner

Profile
conditioner

V-T
V-T
R
out
R
cal
R
iv
V
in
.
1 V
in
R
out
R
cal
R
iv
V
in
.
1 V
in
simplify
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12/4/2002 Introduction
Simplify for example
Control
PWL VCCS
I-V
Vss
Control
PWL VCCS
I-V
Vdd
0 V 0 O
1 V O
0 V 0 O
1 V O
Buffer Pad
Write
enable
Bit
Pattern
Voltage-
Time
Profile
Generator
1.0 V
1.0 V
Profile
conditioner

Profile
conditioner

V-T
R
out
R
cal
R
iv
V
in
.
1 V
in
R
out
R
cal
R
iv
V
in
.
1 V
in
V-T
Rise
Fall
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12/4/2002 Introduction
Voltage-Time Profile Generator
Positive Edge Voltage
Profile Generator
Rising
VT
Voltage controlled
voltage source
Ramp voltage
used to look up
output voltage
base on v-t table
Falling
VT
H

Falling
Volt - Time
Ramp
Generator


Rising
Volt - Time
Ramp
Generator

1.0 V
1.0 V
1.0 V
Data in
Delay falling edge
by falling edge
transition time
Negative Edge Voltage
Profile Generator
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12/4/2002 Introduction
Voltage Time Ramp
The voltage-time ramp is a ramp that
starts at a specified time and whose
voltage is proportional to the time from
the specified starting point.
In our case, we will create a voltage-
time ramp on the detection of each bit
edge transition.
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12/4/2002 Introduction
Explore the voltage across a capacitor
If current, I is
constant and is equal
to the capacitance,
then the voltage
across the capacitor
is equal to time.
If the I does not
equal C, the voltage
is across the
capacitor
proportional to I/C.
V t
I
C
d
if I = C
V t 1d T
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12/4/2002 Introduction
Define Characteristics of voltage time ramp
A unity voltage time ramp is when I/V = 1 so that
t1=v1
Since this voltage is usually small, I/C may be set to
1e9. This means 1 nanosecond corresponds to 1 volt.
V
t
relative t=0 Time=t1
v1=I/C*t1
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12/4/2002 Introduction
Circuit to create unit ramp
The one input of a
differential amp is
connected to a dc
reference and the
other input is our
input pulse wave.
The switch shorts
the cap at t=0 and
opens when the edge
is detected.
1 pA
1 pF
1 V
V t
I
C
d
if I = C
V t 1d T
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12/4/2002 Introduction
in
In delayed
E

2
edge in
progress
out
X
Delay falling edge .. digitally well almost
Since we will use a
threshold detector
to determine an
edge, we can add
signals together and
only use the portion
of the signal that we
deem important.
Triggering at the
reference threshold
delays the negative
edge
Threshold
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12/4/2002 Introduction
Put the circuit together for positive edge ramp.
The processed signal is
used to drive the switch
which in turn creates the
positive edge ramp.

1 pA
1 pF
1 V
1nV = 1 nS after positive edge
THRESHOLD_0_1_DETECT
in
In delayed
E

2
edge in progress
out
X
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12/4/2002 Introduction
Put the circuit together for negative edge ramp.
The negated data is used
to drive the switch which
in turn creates the
negative edge ramp.

1 pA
1 pF
1 V
1nV = 1 nS after positive edge
THRESHOLD_0_1_DETECT
in
In negated
out
X
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12/4/2002 Introduction
Positive Voltage-Time Ramp
Generator HSPICE CODE
* delay in by tf
Edelay in_delayed 0 DELAY in 0 TD='tf'
* create step shaped waveform for delaying by tf
Equalify_r edge_in_progress 0
+ VOL='V(in)+V(in_delayed)'
* switch on edge in progress is above 0.5 v
Gswitch_r shunt_c_r 0
+ VCR PWL(1) edge_in_progress 0 .5v,.00001 .501v,1g
Vone_volt one_volt 0 100v
* charge rate is 1v/ns (I/C)
Ccharge_r shunt_c_r 0 1pf
Icharge_r one_volt shunt_c_r 1ma
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12/4/2002 Introduction
Negative Voltage-Time Ramp
Generator HSPICE CODE
* Create complement of in
Eneg_in in_bar 0 vol='1-v(in)'
* switch on edge in progress is above 0.5 v
Gswitch_f shunt_c_f 0
+ VCR PWL(1) in_bar 0 .5v,.00001 .501v,1g
* charge rate is 1v/ns (I/C)
Ccharge_f shunt_c_f 0 1pf
Icharge_f one_volt shunt_c_f 1ma
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12/4/2002 Introduction
Map ramp to V-T data with
By driving the ramp
into the control node
of equation
controlled voltage
source, time on the
ramp is mapped to
voltage.
This control voltage
ranges from 0v to 1V
is geometrically
similar to the
desired edge
V
relative
t=0
t
x
=v
x
V
relative
t=0
t
x
=v
x

V(v)=V(t)
Edge rate
t
t
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12/4/2002 Introduction
Mapping with PWL VCVS
Time is scaled to
the edge rate
This is the data
for the
corresponding
edge shape
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12/4/2002 Introduction
Putting edge together with v-t data
H
.SUBCKT VT_RISE_GEN_mid_n in out out_ref

Edatar out out_ref PWL(1) in 0

+ '0.000*Tr_mid_n' 0.000
+ '0.185*Tr_mid_n' 0.006
+ '0.315*Tr_mid_n' 0.017
+ '0.398*Tr_mid_n' 0.030
...
+ '0.917*Tr_mid_n' 0.988
+ '0.944*Tr_mid_n' 0.994
+ '0.991*Tr_mid_n' 0.999
+ '1.000*Tr_mid_n' 1.000
.ENDS VT_RISE_GEN_mid_n

Voltage Controlled Voltage Sources
.SUBCKT VT_FALL_GEN_mid_n in out out_ref
Edatar out out_ref PWL(1) in 0

+ '0.000*Tf_mid_n' 1.000
+ '0.023*Tf_mid_n' 0.996
+ '0.034*Tf_mid_n' 0.985
+ '0.057*Tf_mid_n' 0.957

+ '0.739*Tf_mid_n' 0.016
+ '0.773*Tf_mid_n' 0.008
+ '0.841*Tf_mid_n' 0.003
+ '0.989*Tf_mid_n' 0.000
+ '1.000*Tf_mid_n' 0.000
.ENDS VT_FALL_GEN_mid_n

Falling V-t
curve
Rising V-t
curve
Fall time
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12/4/2002 Introduction
Behavioral methods can be
expanded to include new features
Buffer Pad
Control
PWL VCCS
Clamp
V-I Table
0 V 0 O
1 V O
Profile
conditioner

R
out
R
cal
R
iv
V
in
.
1 V
in
Vdd
Clamp
Voltage
Profile
Generator
1.0 V
Clamp
V - T (voltage)
Wave
0-1V
V Rev
Vss
+
-
Write
enable
Profile
conditioner

R
out
R
cal
R
iv
V
in
.
1 V
in
Dynamic Clamp
31
12/4/2002 Introduction
Voltage-Time Profile Generator Review
Positive Edge Voltage
Profile Generator
Delay negative
edge
by negative
edge
transition time
Positive
V - T (voltage)
Wave
0-1V
Voltage controlled
voltage source
Ramp voltage used to
look up output voltage
base on v-t table
Caveat: any ramp
value > edge time
returns 1 volt
Negative Edge Voltage
Profile Generator
Negative
V - T (voltage)
Wave
0-1V
H
Negative
Volt - Time
Ramp
Generator
V=time
after edge

Positive
Volt - Time
Ramp
Generator
V=time
after edge

Waveform Voltage Profile*
Bit
Pattern
1.0 V
1.0 V
1.0 V
* P profile is the 180 degrees out of phase
compared to the N profile
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12/4/2002 Introduction
Voltage Profile Resistance Conditioner
Goal: Create V-T Profile
that produces a
geometrically similar
waveform at Vout
Limitation: Loads need in
the range of R
tcal
Vout
R
vt

R
iv

R
tcal

Voltage controlled resistor
R
vt
V
out
R
t cal
R
iv
.
1 V
out
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12/4/2002 Introduction
Assignment 2 Create HSPICE Buffer Model
Rp = 100 ohms, Rn=10 ohms
Rise time 20%-80% 1.5 ns when driving a 50
ohms load ground
You need to adjust the pulse transition time
You should use sweep results in you report.
Use wave shape as follows
'(1-exp(-1*(pwr(abs(v(in))*2.4,wf))))'
wf=2, v(in) is pulse wave
Vcc = 2.5 V, Vss = 0 V
Check simulation against calculations of Vol
and Voh with 50 ohm to Vss load
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12/4/2002 Introduction
Key Techniques To Remember
Unity time voltage ramp
PWL Voltage control voltage source
creates V(t) edges.
Simple buffers can be created by using
switches in place of voltage controlled
resistors.