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Based on Digital Systems Design Using VHDL, Chapter 5, by Charles H. Roth, Jr.
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ASM Charts
Three equivalent terms
State Machine (SM) chart State Machine Flowchart Algorithmic State Machine (ASM) chart
Decision box (Condition check box): contains condition Conditional output box: contains conditional output list (or RTL Statements)
Incorrect
correct
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Multiplicand Multiplier
1101 (13) 1011 (11) 1101 1101 100111 0000 100111 1101 10001111 (143)
Initial contents of register 0 0 0 0 0 1 0 1 1 (11) (add multiplicand; M=1) after addition after shift (add multiplicand; M=1) after addition after shift (skip add: M=0) 1101 011011011 001101101 1101 100111101 010011110
after shift
(add multiplicand; M=1) after addition after shift
001001111
1101 100011111 0 1 0 0 0 1 1 1 1 (143) 11
Example 1: Continued
This type of multiplier is called serial-parallel multiplier. (multiplier bits are processed serially, but the addition takes place in parallel) The lower four bits in the accumulator is initially used for storing multiplicand.
Initial contents of register 0 0 0 0 0 1 0 1 1 (11) (add multiplicand; M=1) after addition after shift (add multiplicand; M=1) after addition after shift (skip add: M=0) 1101 011011011 001101101 1101 100111101 010011110
after shift
(add multiplicand; M=1) after addition after shift
001001111
1101 100011111 0 1 0 0 0 1 1 1 1 (143) 12
Example 1: Continued
ASM Chart for the control unit. A external counter is needed for counting the number of shifts. Inputs
St (Start) M K (# of shifts=4)
Output signals:
Load Sh (Shift) Ad (Add) Done
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Example 1: Continued
Conversion of an ASM chart to a VHDL code is straightforward.
CASE statement for each state. Condition box corresponds to an IF statement.
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Flowchart
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Conditions:
D7 D711 (Sum is 7 or 11) D2312 Eq (Sum = Point)
Outputs:
Roll Sp (Sum to be stored) Win Lose
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Contents
Manual state machine design
How to design state machines for complex synchronous sequential digital logic circuits
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Allow more complicated checks for state transitions Uses RTL statements within the states
Within one state, all RTL statements execute concurrently
Permits systematic conversion from algorithms to H/W Variation of State Machine Method
Algorithmic State Machine (ASM) Method
Uses a graphical notation referred to as an ASM chart
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Algorithms
Formal definition of an algorithm
A general step-by-step procedure for solving a problem that is CORRECT and TERMINATES.
Properties of an algorithm
Well-ordered: There is a clear order in which to do the operations. Unambiguous: Each operation is clearly understood by all intended computing agents. Effectively computable: The computing agent has ability to carry out each operation. Finite time: Each operation takes finite time and there will be a finite number of steps.
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Datapath Section
all logic not included in the control logic section
registers, adders, counters, multiplexers, etc.
typically the word-sized data manipulation and storage components through which the data flows
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(3) Datapath
design the datapath based on the RTL Program
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RTL Program
HDL Format
Like a pseudocode description, except that each step is one state of the state machine
All operations within one state execute concurrently
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2. If there is a variable that is assigned different values at different points in the RTL program, then a multiplexer or a tristate bus structure is necessary.
fact is either initialized or have the value fact*count
3. Accepts Control signal inputs to control the operation of the various datapath components. 4. Produce Status signal outputs to Control logic. 5. A few optimizations may be possible by combining registers, adders or other components.
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Status Signals
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One-FF-Per-State Method
Uses one-to-one transformations from state diagram to digital logic components
Also applicable to ASM charts
Transformations
state in state diagram
transforms to a D flip-flop
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For the Control logic design, a state diagram is helpful. The state diagram here is restrictive diagram than formal Finite State Machine (FSM).
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Handshake protocols
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ASM Chart
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Example2:
req is output. data_to_be_sent, ready and ack are inputs. There is only one variable in the pseudocode: DATA
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Form a state diagram with states and control signal activations Derive the control logic design
one-hot or PLD-based approach
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Contents
Manual state machine design
How to design state machines for complex synchronous sequential digital logic circuits
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3. Use a synthesis tool to convert the HDL code into a working hardware circuit.
Implement for the target hardware architecture.
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Used to communicate between two circuits in different clock domains (i.e., clocked by different clock signals)
In large or high-performance circuits, different circuits (or subcircuits) will use different clock inputs because of clock synchronization difficulties or simply because they are independent circuits Communication of data packets between such circuits requires a handshaking protocol
Solution implemented using the automatic synthesis-based method instead of the manual state machine design method used in Example 5.2
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Pseudocode
1. req 0; while (TRUE) do 2. wait until (ready = 1); -- data ready 3. data data_to_be_sent; 4. req not req; -- invert req value 5. wait until (ack = req); end while;
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