Presented by

VINOD.N.A
Roll no. 92
c.s ‘b’
contents
Introduction
Working
Terminology
Development
Commercial incentives
Advantages
Disadvantages
Hardware trend
Software impact
References
Introduction….
Quad-core technology provides outstanding
performance and breakthrough energy
efficiency

It delivers four complete execution cores

within a single processor

It enables greater computing experiences

Contd…..
Powering today’s servers and workstations

Redefining the way you experience desktop

computing
Working…
In quad-core processor all cores lies in a
single die. Cores in quad-core processor may
share a single coherent cache at the highest
on device cache level or may have separate
caches.

The processor also share the same

interconnect to the rest of the system.

Each core independently implements

optimization such as superscalar execution,
pipelining and multithreading.
The amount of performance gained by the
use of processor depends on the problem
being solved and the algorithm used.

The processor will multitask better since it

can run four programs at once, one on each
core.
Terminology..
Most commonly they are used to
refer to some sort of central
processing unit, but sometimes also
applied to digital signal processors
and system on a chip
Development..
Technology continues to improve, reducing
the size of single gates, physical limits of
semiconductor based microelectronics have
become a major design concern.

Instruction level parallelism methods like

superscalar scaling are suitable.

Main purpose of quad-core processor is to

increased thread level parallelism(TLP).
Commercial incentives…
Main motive for quad-core processors comes
from greatly demised gains in processor
performance from increasing the operating
frequency. So
for performance improvements INTEL and
AMD have turned to quad-core design
sacrificing lower manufacturing cost for higher
performance in some applications and
systems.
Advantages…
The proximity of multiple CPU cores on the
same die allows the cache coherency circuitry
to operate at a much higher clock rate than is
possible if the signals have to travel off-chip.

Combining equivalent CPU’s on a single die

significantly improves the performance of
cache snoop operations.

The quad-core CPU designs require much less

printed circuit board space than multi-chip
SMP designs.
Contd…
Quad-core processor uses slightly less power
than four single-core processors.

It produce a product with lower risk of design

error.
Disadvantages…
In addition to operating system support
,adjustments to existing software's are required to
maximize utilization of the computing resources
provided by quad-core processors.

The ability of quad-core processors to increase

application performance depends on the use of
multiple thread.

Integrating of a multicore chip devices production

yields down and they are more difficult to manage
thermally than lower density single chip designs.
Contd…
Processing cores share the same system bus
and memory bandwidth limits the real-world
performance advantage.
Hardware trend…
Development to quad-core processor
improves energy efficiency by focusing on
performance per watt with advanced fine-
grain or ultra fine grain power management
and dynamic voltage and frequency scaling
which is of particular interest for mobile
computing.
Software impact…
Software benefits from multi core architecture
where code can be executed in parallel.

Under most common operating system this

requires code to execute in separate threads
or processes

Parallel programming techniques can benefit

from quad-core directly.
Managing concurrency acquires a central role in
developing parallel applications.

Basic steps in designing parallel applications…

Partitioning-The partitioning stage of a design
is intended to expose opportunities for
parallel execution.
Communication-The computation
to be performed in one task will typically
require data associated with another task
.Data must then be transferred between
tasks so as to allow computation to proceed.
 Agglomeration-we revisit decisions made in
partitioning and communication phases with a
view to obtaining an algorithm that will
execute efficiently on some class of parallel
computer.

 Mapping-In this stage of parallel algorithm

design process ,we specify where each task is
to execute .This mapping problem doesn’t
arise on uniprocessors or on shared memory
computers that provide automatic task
scheduling.
References…
www.intel.com
www.wikipedia.com
THANK
S