65-nm CMOS TECHNOLOGY

Under the guidance of Prof. Raju Yanamshetti

CONTENTS
Introduction What is CMOS 65-nm CMOS technology High gain double bulk mixer in 65-nm CMOS A 65-nm CMOS Ultra low power LC quadrature VCO Processor using 65-nm manufacturing technology Conclusion References

INTRODUCTION
The electronic revolution would not have been made feasible without the invention of CMOS devices While designing the analog and digital ICs it is important to understand the possibilities and limitation of CMOS devices Scaling of CMOS devices to nanometer dimensions for faster circuit operation, high packaging density and low power dissipation For highly scaled MOSFETS is the increase in the source/drain series resistance due to swallow junctions.

What is CMOS?
Complementary metaloxidesemiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. Also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Two important characteristics of CMOS devices are high noise immunity and low static power consumption

Cross section of two transistors in a CMOS gate, in an N-well CMOS process

 Comparison of BJT and MOSFET technology from an analog viewpoint

FUNDAMENTAL PROCESSING STEPS Basic steps Oxide growth Thermal diffusion Ion implantation Deposition Etching Epitaxy

A 65-nm CMOS TECHNOLOGY

The 65 nm process is an advanced lithographic node used in volume CMOS semiconductor fabrication. Features of 65 nm CMOS Gate length : 30 nm (high-performance) to 60 nm (lowpower) Core voltage : 1.0 V Metal 1 pitch : 180 nm Nickel silicide source/drain Gate oxide thickness : 1.9 nm (n), 2.1 nm (p)

 There are actually two versions of the process : CS200, focusing on high performance, and CS200A, focusing on low power. Ultra-high-speed performance (CS200) LG = 30nm, on-current enhance Compared to 90nm technology, CS200 offers: 1.3 times faster speed 0.6 times lower power 2 times higher density

CS200/A transistor variations

HIGH-GAIN DOUBLE-BULK MIXER IN 65 nm CMOS

The mixer consumes only 830 W at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The operation principle of the double-bulk mixer is based on two complementary mixers. The additional PMOS mixer operates as the active load of the NMOS mixer, and the NMOS mixer forms the active load of the PMOS mixer

 The RF input is applied to the gate at both mixer stages, while the clock signal LO is applied to the bulk terminals of both mixer stages.

Both signals are differential. The LO is applied to the bulk to achieve a high gain in the circuit. The bulk connection is done in the layout with a ringcontact around the entire transistor. This is possible for both NMOS and PMOS in the used triple-well technology.

 A common mode feedback, which senses the output common-mode voltage, is necessary to keep the bias condition of the circuit constant within process corners and operation temperature range. The adjusted DC bias voltage of the LO signal controls the gate voltage of the input transistors to a level to keep the bias current constant and the output voltage at VDD/2. The DC voltage at the RF input applied to the bulk can be adjusted externally via an additional pin VB.

Schematic of the proposed double-bulk mixer with common-mode feedback

Schematic of the mixer including the cascade stage.

Layout plot and (b) photograph of the fabricated chip bonded to the measurement board

Measurement results: (a) gain versus supply voltage at 1.5 GHz and (b) gain versus clock frequency (VDD=1.2 V).

A 65 nm CMOS ULTRA-LOW POWER LC QUADRATURE VCO

An ultra-low-power LC quadrature VCO (QVCO) is presented. It is designed in a single-poly seven-metal 65nm CMOS process.

To minimize power dissipation an inductor with a high

LQ product of 188nH at 2.4GHz, and a self-resonant frequency (fo) of 3.8GHz, was designed.

Negative-resistance VCO

LOW-POWER LC VCO DESIGN

A typical negative-resistance LC VCO with a crosscoupled pair connected in parallel to the LC tank to compensate the loss. R' is the equivalent resistance contributed by the inductor. In order to start oscillation, the start-up gain of the oscillator must be larger than unity, which gives

Usually, Astart-up is set to at least 2-3 to have some margin

 Since the amplitude of the fundamental component of a square wave is 4/_ times the amplitude of the square wave

Hence the differential peak output voltage is

 Above are very important to power consumption of oscillators, and they show that the bias current is inversely proportional to R', where:

The result is that in order to minimize the power consumption the LQ product of the inductor must be maximized.

Integrated Inductor
The single- lumped model was adopted because of its simplicity. Instead of using two separate spiral inductors, the use of a single center-tapped inductor gives the benefit of higher inductance at a given area
The expression for spiral inductance

 where 0 is the permeability of free space, n is the number of turns, ci are layout dependent coefficients, fill and davg are the fill ratio and average diameter, respectively, given by:

Center-tapped octagonal inductor and (b) its single- lumped model.

Varactor

. C-V characteristics of (a) inversion-mode and (b) accumulation-mode varactor.

 C-V curves of accumulation-mode and inversionmode varactors. The inversion-mode varactor is more favorable for low-power applications because of its sharper transition
The sharper transition also means they are more sensitive to substrate noise thus it may be necessary to put the varactor inside a deep n-well to avoid the noise coupling. nMOS is used because electrons have higher mobility than holes, hence a lower series resistance is obtained

QUADRATURE VCO
The reference current source is implemented off-chip to provide more freedom to control the measurement. M5M8 are the coupling transistors. Coff-chip is added to filter out the noise contributed by the reference current source and the transistor M11. Open-drain buffers M12M15 are added to output the quadrature signals off-chip. C1C4 are nMOS inversion-mode varactors. Cross coupled nMOS negative-resistance pairs are used as they have better driving ability at a given area than their pMOS counterparts.

Overall schematic of QVCO

PROCESSORS USING 65 nm MANUFACTURING TECHNOLOGY

Intel Pentium 4 (Cedar Mill) 2006-01-16 Intel Pentium D 900 series 2006-01-16 Intel Celeron D (Cedar Mill cores) -2006-05-28 Intel Core-2006-01-05 Intel Core 2-2006-07-27 Intel Xeon (Sossaman)-2006-03-14

Microsoft Xbox 360 Falcon: CPU-2007-09 Microsoft Xbox 360 Opus CPU-2008 Microsoft Xbox 360 Jasper CPU-2008-10

CONCLUSION
The 65 nm low power technology is a conventional gate stack architecture where process simplicity, low cost, high density, high reliability and reduced consumption are the key focal points. 65 nm CMOS technology offers the next step for SoC designers seeking improved performance as well as low power consumption

REFERENCES
High-Gain Double-Bulk Mixer in 65 nm CMOS with 830 Mw Power Consumption Kurt Schweiger and Horst Zimmermann. A 65 nm CMOS Ultra-Low-Power LC Quadrature VCO Kin Keung Lee, Carl Baryant, Markus Tormanen, Henrik Sjoland http://www.ais.fraunhofer.de/~surmann/papers/IEEE-trans96.pdf http://en.wikipedia.org/wiki/CMOS 65 nm CMOS Process Technology, Paul Kim, Senior Manager, Foundry Services, Fujitsu Microelectronics America, Inc.<http://members.fortunecity.com/templarser/65nm CMOS.html http://en.wikipedia.org/wiki/65nmCMOS