By SHUVRA SAHA

Contents
Why Flash Memory?

Differences Between EPROM,EEPROM and Flash Memory Cell. Usage of Flash memory cell in todays market.

Principles of Floating Gate Device. Charge Injection Mechanism.

Hot Electron Injection.

Fowler-Nordheim Tunneling.

Industry-Standard Flash Cells

Basic Operations
a. Read.
b. Program. c. Erase.

 Reliability
a) b) c)

d)

Programming Disturb. Retention. Endurance. Erase Distribution.

Scaling Issues.

Flash Array Architectures.

Nor and Nand. Parallel and Serial.

Block Diagram of Flash Memory Cell along with peripheral circuitry. Conclusion.

Two type of CMOS Memory: 1)RAM: Information is lost once the power supply is switched off. They are therefore volatile. a)SRAM b)DRAM 2)ROM: They are non-volatile i.e. they keep information stored also when the power supply is switched off. a)EPROM: Electrically Programmable Read Only Memory. b)EEPROM: Electrically Erasable and Programmable Read Only Memory. c)Flash Memory.
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Comparative Study Of NVMs

Why Flash?
EPROM Electrically Programmable but erasable via exposure to UV. Single transistor cell. Density is more. Programmed by CHE injection but erased by UV light. Single bit programmable but erase on the whole array. EEPROM Both electrically programmable and erasable. Two transistor cell. Density is less and occupies more area. Both programmed and erased by FN tunneling. They allow byte alterability. Flash Cell Both electrically programmable and erasable. Single transistor cell. Density is more. Mostly programmed CHE injection but erased by FN tunneling. Single bit programmable and erase consist of large no. of cells together(sector or block).
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Usage of Flash

Floating Gate Device

Charge Injection Mechanism

HOT ELECTRON INJECTION(mostly used for

programming operation).

FOWLER-NORDHEIM TUNNELING(mostly used for

erasing operation).

Hot Electron Injection

Fowler-Nordheim Tunneling
An optimum thickness(10nm) is chosen to trade off between performance and reliability.

Industry Standard Flash Cell(ETOX)

The Cell is asymmetrical

EPROM TUNNEL OXIDE

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Basic Operation On Flash Memory Cell

Operation READ PROGRAM ERASE(DV)

Source GND GND Vpp

Control Gate Vcc Vpp GND

Drain Vread Vdd FLOAT

ERASE(SV)

Vcc

Vneg

FLOAT

Vcc=5v,Vpp=12v,Vdd=5-7v,Vread=1v,Vneg=-8v

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Source breakdown is one of the major limiting factors to erase time reduction

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Reliability

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Oxide Defects and Ionic Contamination

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Scaling
Reduction in Leff.

Reduction in operating voltages.

Limitation on tunnel oxide thickness to 7-8nm and

interpoly dielectric to be around 12-13nm.

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NOR architecture

NAND architecture

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General Architecture of Flash Memory System

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Flash Chip

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To be continued

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THANK YOU

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