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Dr Musharraf A Hanif
Review of interrupt in general Interrupt structure on the STM32F100 Cortex-M3s Nested Vector Interrupt Controller (NVIC) NVICs registers Enabling a specific interrupt Sample code for a timer interrupt
Interrupt Review
Interrupts are an asynchronous signal generated by a peripheral to obtain the CPUs attention urgently. In response to an active / pending interrupt, the processor runs the corresponding interrupt service routine (ISR). The context has to be saved at the start of the ISR and restored at the end of the ISR. The address for the interrupt service routines are stored in a vector table. In the STM32F100, the vector table is in the startup file, while the context switching is managed by the hardware.
3 by Dr. Musharraf A Hanif
The various peripherals on the STM32F100 can generate an interrupt signal. These interrupt signals are connected to the CortexM3s Nested Vector Interrupt Controller.
Timer 1 Timer 2 ADC USART 1 SPI 1 ...
4 by Dr. Musharraf A Hanif
CPU
Configure peripheral to generate an interrupt signal (peripheral registers). Enable the corresponding interrupt in the NVIC (NVIC registers). Ensure that the ISR function has the same name as the entry for that interrupt source in the vector table.
Cortex M3 Technical Reference Manual (chapter 6, page 62) ARMv7 Architecture Reference Manual (section B3.4, page 750)
How to configure the timer to generate an interrupt at the timer peripheral? How to set the correct bit in the interrupt enable registers? What name to use for the ISR function?
if(PERIOD > 1)
{ } TIM2_PSC = 7999; TIM2_ARR = PERIOD - 1; //prescaler for 1ms //interrupt after PERIOD ms
else
{ } TIM2_PSC = 799; TIM2_ARR = 9; //prescaler for 1e-4 s //interrupt after PERIOD ms
Main function
int main(void) { RCC_APB2ENR |= 0x00000010; RCC_APB1ENR |= 0x00000001; Tim_2_Init(500); LED_Init(); while(1) { } return(1); } //enable clock to GPIO port C //enable TIM2
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