Lexical Conventions Data Types

Very similar to C
Verilog is case-sensitive All keywords are in lowercase
Whitespace Comments Numbers Strings Identifiers Keywords

Whitespace

Whitespace is ignored in Verilog except

In strings When separating tokens

Blank space (\b) Tab (\t) Newline (\n)

Comments

// single line comment /* multi-line comment */ /* Nested comments /* like this */ may not be acceptable (depends on Verilog compiler) */

Used for readability and documentation Just like C:

Arithmetic Logical Relational Equality Bitwise Reduction // Not available in software languages Shift Concatenation Replication Conditional

Number Specification
Sized numbers Unsized numbers Unknown and high-impedance values Negative numbers

X or Z values

Unknown value: lowercase x

High-impedance value: lowercase z Examples

12h13x 6hx 32bz

4 bits in hex, 3 bits in octal, 1 bit in binary 4 bits in hex, 3 bits in octal, 1 bit in binary

Extending the most-significant part

Filled with x if the specified MSB is x Filled with z if the specified MSB is z Zero-extended otherwise 6hx

Applied when <size> is bigger than the specified value

Examples:

Negative numbers
-6d3 4d-2 // illegal

Put the sign before the <size> Examples:

Twos complement is used to store the value Use _ to improve readability

Underscore character and question marks

? is the same as z (only regarding numbers)
4b10?? // the same as 4b10zz 12b1111_0000_1010 Not allowed as the first character

Strings

As in C, use double-quotes Examples:

Hello world! a / b text\tcolumn1\bcolumn2\n

Identifiers and keywords

identifiers: alphanumeric characters, _, and $

Keywords: identifiers reserved by Verilog Examples:
reg value; input clk;
Should start with an alphabetic character or _ Only system tasks can start with $

Value set and strengths Nets and Registers Vectors Integer, Real, and Time Register Data Types Arrays Memories Parameters Strings

Verilog concepts to model hardware circuits

Value level Value strength

Used to represent connections between HW elements Keyword: wire

Default value: z Examples Values continuously driven on nets Fig. 3-1 Default: One-bit values
unless declared as vectors
For trireg, default is x wire a; wire b, c; wire d=1b0;

Registers represent data storage elements

Retain value until next assignment NOTE: this is not a hardware register or flipflop Keyword: reg Default value: x Example:
reg reset; initial begin reset = 1b1; #100 reset=1b0; end

Net and register data types can be declared as vectors (multiple bit widths) Syntax: Example
wire/reg [msb_index : lsb_index] data_id; wire a; wire [7:0] bus; wire [31:0] busA, busB, busC; reg clock; reg [0:40] virtual_addr;

Integer

Keyword: integer Very similar to a vector of reg

Bit width: implementation-dependent (at least 32bits)

Designer can also specify a width:
integer [7:0] tmp;

integer variables are signed numbers reg vectors are unsigned numbers

Examples:

integer counter; initial counter = -1;

Real

Keyword: real Values:

Cannot have range declaration Example:

Default value: 0 Decimal notation: 12.24 Scientific notation: 3e6 (=3x106)

real delta; initial begin delta=4e10; delta=2.13; end integer i; initial i = delta; // i gets the value 2 (rounded value of 2.13)

Time

Used to store values of simulation time Keyword: time Bit width: implementation-dependent (at least 64) $time system function gives current simulation time Example:
time save_sim_time; initial save_sim_time = $time;

Only one-dimensional arrays supported Allowed for reg, integer, time Syntax:
Not allowed for real data type
<data_type> <var_name>[start_idx : end_idx];

Examples:

integer count[0:7]; reg bool[31:0]; time chk_point[1:100]; reg [4:0] port_id[0:7]; integer matrix[4:0][4:0]; // illegal count[5] chk_point[100] port_id[3]

Note the difference between vectors and arrays

RAM, ROM, and register-files used many times in digital systems Memory = array of registers in Verilog Word = an element of the array Examples:
Can be one or more bits

Note the difference (as in arrays):

reg membit[0:127]; reg [0:127] register;

reg membit[0:1023]; reg [7:0] membyte[0:1023]; membyte[511]

Similar to const in C Syntax:

But can be overridden for each module at compiletime

parameter <const_id>=<value>;

Gives flexibility
Example:

Allows to customize the module

parameter port_id=5; parameter cache_line_width=256; parameter bus_width=8; wire [bus_width-1:0] bus;

Strings are stored in reg variables. 8-bits required per character The string is stored from the least-significant part to the most-significant part of the reg variable Example:
reg [8*18:1] string_value; initial string_value = Hello World!; \n: newline %%: % \: \t: tab \\: \ \ooo: character number in octal

Escaped characters

Basic structure of a Verilog module:

module mymod(output1, output2, input1, input2); output output1; Verilog convention lists output [3:0] output2; outputs first input input1; input [2:0] input2; endmodule

Instances of

module mymod(y, a, b);

look like

mymod mm1(y1, a1, b1); // Connect-byposition mymod (y2, a1, b1), (y3, a2, b2); // Instance names omitted mymod mm2(.a(a2), .b(b2), .y(c2)); // Connect-byname