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Computer System Architecture

M. Morris Mano

guiseok@yahoo.com

Computer System Architecture Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

Class Overview

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First Course in Computer Hardware Learn how a computer actually works Build the Mano Machine Learn one computer in detail, others are mastered easily. Homework:
Solve the even number of problems Due at the beginning of the next class

Optional Mano Machine Design Report Grade:

Homework(20%) Optional Report(10%) Mid/Final Exam(each 30%)

Class Participation(10%)

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

8 Student Types

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Insecure: 25 % Silent: 20 % Independent: 12 % Friendly: 11 % Obedient: 10 % Heroic: 9 % Critic: 9 % Unmotivated: 4 % - Michigan State University

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-1 Digital Computers

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Computer = H/W + S/W Program(S/W)

A sequence of instruction S/W = Program + Data The data that are manipulated by the program constitute the data base Application S/W DB, word processor, Spread Sheet System S/W OS, Firmware, Compiler, Device Driver

Application S/W

API Operating System

ROM BIOS

Computer H/W

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-1 Digital Computers

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continued

Computer Hardware
CPU Memory Program Memory(ROM) Data Memory(RAM) I/O Device Interface: 8251 SIO, 8255 PIO,
6845 CRTC, 8272 FDC, 8237 DMAC, 8279 KDI

Memory

CPU

Input Device: Keyboard, Mouse,

Scanner

Output Device: Printer, Plotter,

Display

Storage Device(I/O): FDD, HDD,

MOD

Input Device

Interface

Output Device

Figure 1-1 Block Diagram of a digital Computer

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-1 Digital Computers

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continued

3 different point of view(Computer Hardware)

Computer Organization(Chap 1 - 4) H/W components operation/connection

Computer Design(Chap 5 - 7) H/W Design/Implementation

Computer Architecture(Chap 8, 9, 11, 12) Structure and behavior of the computer as seen by the user Information format, Instruction set, memory addressing, CPU, I/O, Memory

ISA(Instruction Set Architecture)

the attributes of a system as seen by the programmer, i.e., the conceptual

structure and functional behavior, as distinct from the organization of the data flows and controls, the logic design, and the physical implementation.

- Amdahl, Blaaw, and Brooks(1964)

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-1 Digital Computers

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What is Computer Architecture?

- Hennessy and Patterson, Computer Organization and Design(1990)

Computer Architecture Instruction Set Architecture (ISA) Machine Organization

ISA?
Instructions, Addressing modes, Instruction and data formats, Register

Machine Organization?
CPU(Control, Data path), Memory, Input, Output

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-2 Logic Gates

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ADC(Analog to Digital Conversion)

Signal

Physical Quantity
V, A, F,

Binary Information Discrete Value

0 : 0.5

1: 3

Gate
The manipulation of binary information is done by logic circuit called

gate.

Fig. 1-2 Digital Logic Gates

AND, OR, INVERTER, BUFFER, NAND, NOR, XOR, XNOR

George Boole
Born: 2 Nov 1815 in Lincoln, Lincolnshire, England Died: 8 Dec 1864 in Ballintemple, County Cork, Ireland

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-3 Boolean Algebra

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Boolean Algebra
Deals with binary variable(A, B, x, y: T/F or 1/0) + logic

operation(AND, OR, NOT)

Boolean Function: variable + operation

F(x, y, z) = x + yz

Truth Table: Fig. 1-3(a)

Relationship between a function and variable x y z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 F 0 1 0 0 1 1 1 1
x y z

Logic Diagram: Fig. 1-3(b)

Algebraic Expression Logic Diagram(gates )

2n Combination

Variable n = 3

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-10

Purpose of Boolean Algebra

To facilitate the analysis and design of digital circuit

Convenient Tools
Truth table : relationship between binary variables

Logic diagram : input-output relationship

Find simpler circuits for the same function

Boolean Algebra Rule : Tab. 1-1

- Operation with 0 and 1: x + 0 = x , x + 1 = 1 , x 1 = x , x 0 = 0
- Idempotent Law: x + x =x , x x = x - Complementary Law: x + x' = 1 , x x' = 0 - Commutative Law: x + y = y + x , x y = y x - Associative Law: x + (y + z) = (x + y) + z , x ( y z) = (x y) z - Distributive Law: x ( y+ x) = (x y) + (x z) , x + (y z) = (x + y) (x + z) - DeMorgan's Law: (x + y)' = x' y , (x y ) = x + y General Form: (x1 + x2 + x3 + xn)' = x1' x2' x3' xn (x1 x2 x3 xn) ' = x1' + x2' + x3' + xn
( A B )c Ac B c

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-11

[]
F= AB + CD + AB + CD

[]
F= ABC + ABC + AC

Fig. 1-6(a)

= x + x (let x= AB + CD) =x = AB + CD

= AB(C + C) + AC Fig. 1-6(b) = AB + AC 1 inverter, 1 AND gate

Fig. 1-4 2 graphic symbols for NOR gate

x y z (x+y+z) x y z x yz

(a) OR-invert

(b) invert-OR

Fig. 1-5 2 graphic symbols for NAND gate

x y z (xyz) x y z (x+y+z)

(a) NAND-invert
Computer System Architecture

(b) invert-NAND
Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.

1-4 Map Simplification

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Karnaugh Map(K-Map)
Map method for simplifying Boolean expressions

Minterm / Maxterm
Minterm : n variables product ( x=1, x=0) Maxterm : n variables sum (x=0, x=1)

2 variables example
x 0 0 1 1 y 0 1 0 1 Minterm x'y' m0 x'y x y' xy m1 m2 m3 Maxterm x+y M0 x + y' x'+ y x'+ y' M1 M2 M3

F = xy + xy

m0 + m1 + m2 + m3

M0 M1 M2 M3

(1,3) (0,2)
Computer System Architecture

m1

m3

( m1 +

m3 ) M2 )
Dept. of Info. Of Computer.

(Complement = M0

Chap. 1 Digital Logic Circuits

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Map
2 variables
B

3 variables
B

4 variables
C

0
A

1 3
A

0 4

1 5
C

3 7

2 6
A

0 4 8

1 5 9
D

3 7

2 6
B

12 13 15 14 11 10

5 variables
0 8
A

1 9

4
B

11 10 14 15 13 12

24 25 27 26 30 31 29 28 16 17 19 18 22 23 21 20
E D F

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

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[] F= x + yz
(1) Truth Table
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 1 0 0 1 1 1 1
Minterm

(2) F ( x, y, z ) (1,4,5,6,7) (3)

y
0 4 1 5 3 7 2 6

m0 m1 m2 m3 m4 m5 m6 m7
z
x

F= x + yz

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-15

Adjacent Square
Number of square = 2n (2, 4, 8, .) The squares at the extreme ends of the
0 4 1 5 3 7 2 6

same horizontal row are to be considered adjacent

The same applies to the top and

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10

bottom squares of a column

The four corner squares of a map must

0
0 4 1 5 3 7 2

1 5 13 9

3 7 15 11

2 6 14 10

be considered to be adjacent
Groups of combined adjacent squares

4
6

12 8

may share one or more squares with one or more group

0 4

1 5

3 7

2 6

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

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[] F ( A, B, C ) (3,4,6,7)
0 1 5
C

3 7
B

2 6

F=AC + BC

[] F ( A, B, C ) (0,2,4,5,6)
F=C + AB
A

0 4

1 5
C

3 7
C

2 6

[] F ( A, B, C, D) (0,1,2,6,8,9,10)
F=C + AB
A

0 4 12 8

1 5 13 9
D

3 7 15 11
C

2 6 14 10
B

Product-of-Sums Simplification F ( A, B, C, D) (0,1,2,5,8,9,10)

F=BD + BC + ACD
Sum of product

0 4 12 8

1 5 13 9

3 7 15 11

2 6 14 10
B

F=AB + CD + BD(square marked 0s) F(F)=(A + B)(C + D)(B + D)

Computer System Architecture

Product of Sum
Chap. 1 Digital Logic Circuits

D Dept. of Info. Of Computer.

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NAND Implementation
Sum of Product : F=BD + BC + ACD
B D C A D

NOR Implementation
Product of Sum : F=(A + B)(C + D)(B + D)
A B C D D

Dont care conditions

F(A,B,C)=(0, 2, 6), d(A,B,C)= F=A + BC=

B
0 1 3 2 6

(1, 3, 5)
A

X X

(0, 1, 2, 3, 6)
Chap. 1 Digital Logic Circuits

C Dept. of Info. Of Computer.

Computer System Architecture

1-5 Combinational Circuits

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Combinational Circuits
A connected arrangement of logic gates with a set of inputs and outputs Fig. 1-15 Block diagram of a combinational circuit

...

in

...

i0 i1

Combinational Circuits (Logic Gates)

f0 f1 fm

Analysis
Logic circuits diagram

Boolean function or Truth table

Experience

Design(Analysis )
1. The Problem is stated

2. I/O variables are assigned

3. Truth table(I/O relation)

4. Simplified Boolean Function(Map Boolean ) 5. Logic circuit diagram

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

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Design Example : Full Adder

1. Full adder is a combinational circuits that forms the arithmetic sume

of three input bit(Carry considered) 2. 3 Input(x, y, z), 2 Output(S: sum, C: carry) 3. Truth Table 4. Simplification
x 0 0 0 0 1 1 1 1 Input y z 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Output C S 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

0
x

1 5
z

3 7

2 6
x

0 4

1 5
z

3 7

2 6

C= xyz + xyz + xy =z(xy + xy) + xy =z(x y) + xy

5. Logic circuit diagram

x y z c

S=xyz + xyz + xyz + xyz = z(xy + xy) + z(xy + xy) = z(x y) + z(x y) =ab + ab (let a=z, b=x y) =x y z

s
Computer System Architecture

(x y)=(xy+xy) =(x+y)(x+y) =xx+xy+xy+yy =xy+xy

Dept. of Info. Of Computer.

Chap. 1 Digital Logic Circuits

1-6 Flip-Flops

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Flip-Flop

Combinational Circuit = Gate Sequential Circuit = Gate + F/F

The storage elements employed in clocked sequential circuit A binary cell capable of storing one bit of information

SR(Set/Reset) F/F
S
SET

Q(t+1) no change clear to 0 set to 1 Indeterminate

D(Data) F/F
D
SET

Q Q

CLR

S 0 0 1 1

R 0 1 0 1

Q Q

Q(t) 0 1 ?

D 0 1

0 1

Q(t+1) clear to 0 set to 1

CLR

no change condition : Q(t+1)=D

: 1) Disable Clock 2) Feedback output into input

JK(Jack/King) F/F
J
SET

T(Toggle) F/F
T
SET

Q Q

CLR

J 0 0 1 1

K 0 1 0 1

Q(t+1) Q(t) no change 0 clear to 0 1 set to 1 Q(t)' Complement

Q Q

T 0 1

Q(t+1) Q(t) no change Q'(t) Complement

CLR

JK F/F is a refinement of the SR F/F The indeterminate condition of the SR

T=1(J=K=1), T=0(J=K=0) JK F/F : Q(t+1)= Q(t) T

Dept. of Info. Of Computer.

type is defined in complement

Computer System Architecture

Chap. 1 Digital Logic Circuits

1-21

Positive clock transition

Edge-Triggered F/F
State Change : Clock Pulse Rising Edge(positive-edge transition) Falling Edge(negative-edge transition)

Setup time(20ns) minimum time that D input must remain at constant value before the transition. Hold time(5ns) minimum time that D input must not change after the positive transition. Propagation delay(max 50ns) time between the clock input and the response in Q gate 2-20 ns setup hold time F/F gate . Master-Slave F/F 2 F/F (Slave Master F/F) negative-edge transition : Race

ts

th

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-22

Race
- Setup time > Propagation delay - 0 1 Unstable - Edge triggered F/F Master/Slave F/F 7470 : J-K Edge triggered F/F 7471 : J-K Master/Slave F/F

Excitation Table
Required input combinations for a given change of state
Present State Next State
SR F/F Q(t) Q(t+1) S 0 0 0 0 1 0 1 0 1 1 1 X R X 1 0 1 JK F/F Q(t) Q(t+1) J 0 0 0 0 1 1 1 0 X 1 1 X K X X 1 0 D F/F Q(t) Q(t+1) 0 0 0 1 1 0 1 1 D 0 1 0 1 T F/F Q(t) Q(t+1) 0 0 0 1 1 0 1 1 T 0 1 1 0

Dont Care

1 : Set to 1 0 : Complement

1 : Clear to 0 0 : No change

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-7 Sequential Circuits

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A sequential circuit is an interconnection of F/F and Gate Clocked synchronous sequential circuit Combinational Circuit = Gate
Sequential Circuit = Gate + F/F

Input

Combinational Circuit Flip-Flops

Output

Clock

Flip-Flop Input Equation

Boolean expression for F/F input Input Equation DA = Ax + Bx, DB = Ax Output Equation y = Ax + Bx

DA

SET

Q Q

A A

CLR

DB
Clock

SET

Q Q

B B

Fig. 1-25 Example of a sequential

circuit

CLR

y
Chap. 1 Digital Logic Circuits Dept. of Info. Of Computer.

Computer System Architecture

1-24

State Table
Input x 0 1 0 1 0 1 0 1
Input Equ.
Next State Output

Input Equ. = Next State

State Diagram
Graphical representation of state

Present state, input, next state, output

Present State

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Ax 0 0 0 0 0 1 0 1

Bx 0 0 0 1 0 0 0 1

DA 0 0 0 1 0 1 0 1

DB 0 1 0 1 0 0 0 0

A 0 0 0 1 0 1 0 1

B 0 1 0 1 0 0 0 0

y 0 0 1 0 1 0 1 0

table Circle(state), Line(transition), I/O(input/output)

0/0 00 0/1 0/1 1/0 10

Design Example: Binary Counter

x=0 0/00 x=0 x=1 10 00

JK F/F Q(t) Q(t+1) J 0 0 0 0 1 1 1 0 X 1 1 X

K X X 1 0

0/1 1/0

1/0

Next State = Output

01

1/0

11

x=1: 00, 01, 10, 11,

00, 01, .. x=0: no change

Excitation Table(2 bit counter = 2 F/F)

Present State

x=1 1/01

x=1

State Diagram:

4 state(00, 01, 10, 11)

01 x=0

x=1

11 x=0

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Input Next State x A B 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0

F/F Input Equ.

JA 0 0 0 1 x x x x

KA x x x x 0 0 0 1

JB 0 1 x x 0 1 x x

KB x x 0 1 x x 0 1

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.

1-25

Map for simplification Input variable: A, B, x

B B
2 6

Logic Diagram
x
SET

JA
A

0 4

1 5

1 X

3 7

KA
A

Q Q

0 4

1 5

X 1

3 7

2 6

CLR

JA=Bx
B

KA=Bx
B
2 1 3

JB
A

0 4

1 X X 5 7 6 1 X X
x

KB
A

X X 4 5 X X
x

1 1

3 7

2 6

SET

Q Q

CLR

JB=x

KA=x

Clock
1. The Problem is stated 2. I/O variables are assigned 3. Truth table(I/O relation) 4. Simplified Boolean Function 5. Logic circuit diagram

Sequential Circuit Design Procedure

1-5 (Combinational Circuit Design) Sequential Circuit 3 State

diagram State table F/F : 2m+n (m - State , n - Input )

Computer System Architecture

Chap. 1 Digital Logic Circuits

Dept. of Info. Of Computer.