LOGO

ANALOG ELECTRONICS II

Mohd Shawal Jadin

FET DC BIASING- Review & Continue

 Learning Objectives
Upon completion
1 of the chapter the student
should be able to:
2
1 Describe various configuration of FET biasing

Analyze various configuration of FET biasing.

2

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Group Discussion

Form a group of 5-6

Write : your group and
members name
Answer all questions in 7
minutes for each
question
10 marks per question +
bonus
ANALOG ELECTRONICS II - BEE2233 FKEE UMP
 Example 1
Find:
VGSQ, IDQ
VG
VD
VDS
VS
IG
 Example 2

Calculate the value of VDS

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Example 3

What is the new

value of RD
when there is 7
V across VDS?

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Example 4

Given the values

of VDQ and IDQ for
this circuit,
determine the
required values
of RD and RS.

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Example 5

Determine the
quiescent values
of ID and VGS.

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Voltage-Divider Bias

IG = 0A in FETs. Unlike BJTs, where IB affected IC; in FETs it is

VGS that controls ID.
ANALOG ELECTRONICS II - BEE2233 FKEE UMP
 Voltage-Divider Bias
Calculations

Using Kirchhoff's Law:

Rearranging and using ID =IS:

Again the Q point needs

to be established by
plotting a line that
intersects the transfer
curve.
ANALOG ELECTRONICS II - BEE2233 FKEE UMP
 Voltage-Divider Q-point
1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Voltage-Divider Bias
Calculations
Using the value of ID at the Q-point, solve for
the other variables in the Voltage-Divider
Bias circuit:

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 Test yourself..
Find IDQ and VGSQ
 Exercise..
Determine Q-point for JFET
 Exercise..
For what value of RD is the
voltage across VDS zero?
 Depletion-Type MOSFETs

Depletion-type
MOSFET bias circuits
are similar to JFETs.
The only difference is
that the depletion-
Type MOSFETs can
operate with positive
values of VGS and
with ID values that
exceed IDSS.

ANALOG ELECTRONICS II - BEE2233 FKEE UMP

 The dc analysis
 Same as the FET calculations
 Plotting the transfer characteristics of the device
 Plotting the at a point that VGS exceeds the 0V or more
positive values
 Plotting point when VGS=0V and ID=0A
 The intersection between Shockley characteristics and
linear characteristics defined the Q-point of the MOSFET
 The problem is that how long does the
transfer characteristics have to be draw?
 We have to analyze the input loop parameter relationship.
 As RS become smaller, the linear characteristics will be in
narrow slope therefore needs to consider the extend of
VG −Vof
transfer characteristics for example GS −V RS = 0
voltage divider
MOSFET,
VGS = VG − I D RS

 The bigger values of VP the more positive values we should

draw for the transfer characteristics
Analyzing the MOSFET circuit for
DC analysis

How to analyze dc
analysis for the
shown network?
 It is a …. Type
network
 Find VG or VGS
 Draw the linear
characteristics
 Draw the transfer
characteristics
 Obtain VGSQ and IDQ
from the graph
intersection
• Plot line for VGS = VG, ID = 0 and ID = 
VG/RS, VGS = 0.

• Plot the transfer curve by plotting 
IDSS, VP and calculated values of ID.

5. Where the line intersects the transfer 
curve is the Q­point.

• Use the ID at the Q­point to solve for 
the other variables in the voltage­
divider bias circuit. These are the 
same calculations as used by a JFET 
circuit.
When RS change…the linear characteristics will change..

• Plot line for VGS = VG, ID = 0 
and ID = VG/RS, VGS = 0
• Plot the transfer curve by 
plotting IDSS, VP and 
calculated values of ID.
• Where the line intersects the 
transfer curve is the Q­
point.
• Use the ID at the Q­point to 
solve for the other variables 
in the voltage­divider bias 
circuit. These are the same 
calculations as used by a 
JFET circuit.
LOGO

Mohd Shawal Jadin