A PRESENTATION ON

VLSI DESIGN

Introduction to VLSI
Stands for Very Large Scale Integration.
Process of creating integrated circuits by combining

thousands of transistor-based circuits into a single chip. Design/Manufacturing of extremely small, complex circuit. Language used for designing VLSI circuit
VHDL Verilog

Basic difference between VHDL and Verilog

VHDL 1. Not Case Sensitive 2. Difficult to learn Verilog 1. Case sensitive 2. Easy to learn

3. Based on Pascal

3. Based on C

3.Software Used in VLSI Design

DSCH
XILINX

ALTERA
MICROWIND

Software Used in VLSI Design (Contd.)

Use of DSCH Three types of designs: Gate Level Design Chip Level Design CMOS Level Design

Software Used in VLSI Design (Contd.)

USE OF XILINX AND ALTERA

Through VHDL and Verilog

Data Flow Behavioral

Structural

Software Used in VLSI Design (Contd.)

USE OF MICROWIND
Microwind Software is used for layout design of various circuits.

VLSI Design Hierarchy

Specify what to design.
Specification

Design an Algorithm implement in software.

to
Algorithm design

Enter the design in computer system, so that it can be compiled by the design software. After completion of entry into computer, simulate to see the result.

Design Entry

Fundamental simulation

Flow diagram

Basic VHDL Code

Library declaration

Entity

Architecture

Configuration

Library Declaration
To declare a LIBRARY (that is, to make it visible to the design)

two lines of code are needed, one containing the name of the library, and the other a use clause. The syntax is as follows:
LIBRARY library_name ; USE library_name.package_name.package_parts ;

At least three packages, from three different libraries, are usually needed in a design :

ieee.std_logic_1164(from the ieee library),

standard (from the std library) , and

work (work library)

Library Declarations
LIBRARY ieee; -- A semi-colon (;) indicates the end of a
statement or a declaration

USE ieee.std_logic_1164.all ;

LIBRARY std ;

- a double dash (--) indicates a comment. USE std . Standard . all ; LIBRARY work ; USE work. all;

 The std_logic_1164 package of the ieee

library specifies a multi-level logic system; Std library is a resource library (data types, text i/o, etc.) for the VHDL design environment; and The work library is where we save our design (the .vhd file, plus all files created by the compiler, simulator, etc.).

STD_LOGIC type
Value Meaning

U
X

Uninitialized
Forcing (Strong driven) Unknown

0 Forcing (Strong driven) 0 1 Forcing (Strong driven) 1 Z High Impedance

W L H - Weak (Weakly driven) Unknown Weak (Weakly driven) 0. Models a pull down. Weak (Weakly driven) 1. Models a pull up. Don't Care

Basic VHDL Code (Contd..)

Library Declaration
Library Library_name; Use library_name.package_name.package_parts;

For exampleLibrary ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;

Basic VHDL Code (Contd.)

Entity & Port Declaration
Entity<entity_ name> is Port (port_name:<direction><data_type>; port_name:<direction><data_type>); End<entity_name>;

For exampleEntity and_gate is Port ( a, b : in std_logic; y : out std_logic); End and_gate;

Basic VHDL Code (Contd.)

Architecture Declaration
Architecture< architecture_name> of <entity_name> is begin . . . . . . . . end architecture_name

Basic VHDL Code (Contd.)

Types of VHDL Architecture

Data flow -It uses concurrent signal assignment statement. - It describes the transfer of data from input to output signals. Behavioral - It is a high level description. - It contains a set of assignment statement to represent behaviour. Structural - Describe the circuit structure in terms of logic gates - Interconnects wiring between logic gates to form a circuit net list.