Digital Electronics

1 LOGIC GATES FLIP-FLOPS REGISTERS ADDERS

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Numbers in a computer:
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In the Microprocessor and memory Bits are stored

electronically Each bit is represented by an electrical signal which is either a high or low voltage level.

high high

1 and low 0 and low

0 1

Normal Logic Inverse Logic

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High and Low

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Transistor Transistor Logic (TTL)

CMOS

1:High
3.5 4.9 Volts 2.0 2.4 Volts
NO MANS LAND 74LSxx NO MANS LAND 74HCxx

0.8 0.4 Volts

0:Low

0.1 1.0 Volts

It is actually a bit more complicated than this since there are different thresholds for inputs and outputs and their noise margins (indicated here in RED)..
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Making a Zero or and One

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How do you actually make a 0 or 1 ?

It is clear that depending upon the position of the J1 switch the line will be either 0 or 1

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Binary Logic
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Once the bits are stored, we want to be able to

perform various operations on the bits The operations which the microprocessor carries out can all be constructed with a few simple circuits The basic building blocks are logic gates

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Binary Logic truth tables

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A B AND

You may

0 0 1 1

0 1 0 1

0 0 0 1

OR

0 0 1 1

0 1 0 1

0 1 1 1

NOT

0 1

1 0

remember from the first year lab the gates AND, OR, NOT Any digital device can be made out of either ORs and NOTs or ANDs and NOTs.

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DeMorgans Theorem
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You can swap ANDs with ORs if at the same time

you invert all inputs and outputs :

Exercise: Write truth table for both and prove that this is correct

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An AND out of NOTs and ORs

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Exercise: Test the claim that you can make any logic

device exclusively out of NOTs and ORs by making an AND out of NOTs and ORs:

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Answer:
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Show that this device has an identical truth table

as the AND gate.

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Exercise: Exclusive OR
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Construct an exclusive OR (XOR) gate using OR, ANDs, and NOT:

A B XOR

0 0

0 1

0 1

1 1

0 1

1 0

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The Exclusive OR
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Solution:

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Storing Zeros and Ones: Registers

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Registers are electronic devices capable of storing 0s or 1s D-FLIP-FLOPs are the most elementary registers can store one bit 8 DFFs clocked together make a one byte register Capable of storing 8 bits

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SR Latch: Set and Reset

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Gate level design of an SR latch

When S* is low and R* High, Q is high (Set) When S* is high and R* is low Q is cleared (Reset) Q and Q* are complements
S* 0 1 R* 1 0 Q 1 0 Q* 0 1

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SR Latch: Hold
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Gate level design of an SR latch

When S* and R* are high both states for Q are possible (and stable) The latch remembers the last state it was in, and holds Q in that state
S* 1 R* 1 Q 1 Q* 0

1
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SR Latch: Dont do this

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Gate level design of an SR latch

When S* and R* are low Q and Q* are no longer complementary The latch can also enter a race condition where it oscillates

S* 0

R* 0

Q 1

Q* 1

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SR Latch: 1 bit memory

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S R H H L H L Q H L L H H Q* L H H L H

Gate level design of an SR latch

H H H L L

Ambiguous but stable

S/R high is ambiguous, but stable This circuit remembers that S went low

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Gated D Latch
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Ensures that S and R are always complementary. When the Clock is high D is set on the outputs of the latch and it is held there when the clock is low Exercise: Fill out the truth table for this circuit.
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D latch timing
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The input Data to the gated D latch appears on the output

(Q)while the clock is high. Sometimes we want to transfer the data into the register only at a specified moment (for example when the clock changes) The D Flip-Flop uses two d-latches to latch the data on the edge (depending on the design either positive or negative) of the input clock
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Master Slave D Flip Flop

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Data is stored in

the Master latch (Qm) when the clock is high When the clock goes from high to low

The data is held in the Master The Data is stored in the slave latch output

The Qs output can

only change when the clock goes from high to low

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A real D-Flip-Flop (DFF)

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CLK

D X X X H L

S L H L H H

R H L L H H

Q H L H H L

One can Set or Reset (Clear) the DFF using S or R When S and R are High, on the rising edge of the clock the data are transferred and stored in Q.
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Qbar L H H L H

X X X

4-bit Register
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A register that stores 4 bits

Data Stored on rising edge of clock in Q0,Q1,Q2,Q3

Data coming in D0,D1,D2,D3

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Byte Register
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Byte coming in

8 bit register in a single

package CLK 74F574 Also contains tri-state outputs

Byte Stored

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Addition with Binary Logic Gates

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Computers carry out addition with binary addition of

bits stored in registers We can build additions of large numbers of bits out of units which add two bits
$3+$4 $3+$C $D+$4 $D+$C

0011
+ 0100 = 0111 $7

0011
+ 1100 = 1111 $F

1101
+ 0100 =10001 $11

1101
+ 1100 =11001 $19

Example: Adding two 4 bit numbers results in a 4 bit number plus one carry bit or effectively a 5 bit number Lets construct this adder from gates
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Additions of two bits: The half adder

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Adding two bits

generates two bits of output

1 Sum Bit S 1 Carry Bit C

A 0 1 0 1 B 0 0 1 1 C 0 0 0 1 S 0 1 1 0

The truth table for this

operation is shown along with an implementation using two gates

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Full Adder
In order to add larger numbers, we

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need to be able to bring the carry from the lower order bits, and add this to the sum The inputs are:

A 0 0 1 1 0 0 1 1

B 0 1 0 1 0 1 0 1

C 0 0 0 0 1 1 1 1

C+ 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

the two bits to be added (A,B) The Carry Bit (C)

The outputs are: The Sum Bit (S) The Carry Out Bit (C+) We can build this from two half

adders and an XOR gate

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Two bit adder

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We can construct logic

that adds more than 1 bit together by using multiple full adder circuits

Exercise: Construct a circuit that adds two two bit words (Ao,A1) and (B0,B1) and produces three Sum Bits (S0,S1,S2)

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Solution
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With the Full adder

building block we can generalize to produce a circuit which adds larger numbers

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Four plus Four bit addition

This can clearly be generalized to any number of bits
There is a problem in building circuits this way as the carry bits need to propogate through the circuit before the answer is correct There are other ways to construct adder circuits which avoid this problem

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Arithmetic Logic Unit (ALU)

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Centre of every

computer Composed of building blocks we have been learning about

Adders Flip Flops Registers

We also need to have a

data bus to move data in and out - we will learn about this soon

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