Memory Technology

CS1251 Computer Organization Carl Hamacher

4/3/2014

Department of Information Technology

Memory Connections
MEM
k
ADDRESS

MAR
REG
DATA_OUT DATA_IN Enable_Out CLK Enable_In

RAM
Write Enable_In1 DATA_IN1 Enable_Out2 DATA_OUT2 DATA_IN2 Enable_In2

Read MFC CLK

DATA_OUT

n
DATA_IN

REG_2PORT
DATA_OUT1 Enable_Out1 CLK

MDR

2k addressable locations n-bit words

MFC = Memory-Function-Completed 4/3/2014 Department of Information Technology 2

Byte Addressability
Word address 0 4
0 4

Byte address
1 5 2 6 3 7

Word address 0 4
3 7

Byte address
2 6 1 5 0 4

. . .
2k-4
2k-4 2k-3 2k-2 2k-1

. . .
2k-4
2k-1 2k-2 2k-3 2k-4

Big-endian assignment (Morotola)

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Little-endian assignment (Intel)

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Step

Clock
MAR_En_In Address MEM_Read MDR_En_In1 Data_Out MFC MDR_En_Out2

Memory Speed
Memory Access Time

Initiation to completion of an operation

e.g. Read to MFC

Memory Cycle Time

Minimum delay between two successive operations Usually slightly longer than the access time Bottleneck of a computer system

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Memory Speed
Memory Latency

Time to transfer a word of data to or from the memory Rate of transfer of blocks of data Product of data rate and width of data bus

Memory Bandwidth

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Memory Types
Random Access Memory (RAM)

Read and Write Fixed time independent of address

Magnetic disks Magnetic tapes Contents (not) lost when power is interrupted
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(Partly) Serial Access Storage Devices

(Non) Volatile Memory

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Memory Organization
Cache Memory (Lsn 19)

Small, fast memory Between (larger, slower) main memory and processor Holds currently active segments of program and data

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Memory Organization
Virtual Memory (Lsn 20)

Data stored in physical locations that have addresses different from those specified in the program Memory control circuitry translates logical address into physical address Used to increase the apparent size of physical memory (using magnetic disks) Pages of words swapped between disk and main memory (RAM)
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Semiconductor RAM

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Static RAM
SRAM

Two inverters cross-connected to form a latch Two transistors connect latch to two bit lines CMOS implementation requires 6 transistors per cell (expensive) Very low power consumption Very fast Used mostly in cache memories

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Asynchronous Dynamic RAM

DRAM

Info stored as charge on a capacitor Charge maintained for only tens of milliseconds Periodic refresh required (adds complexity) Higher density Lower cost Predominant in main computer memories

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Synchronous DRAM
SDRAM

Synchronized with a clock signal Address and data connections buffered with registers e.g. PC133 SDRAM (133 MHz bus)

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Double-Data-Rate SDRAM
DDR SDRAM

Transfers data on both clock edges

Latency same as SDRAM Bandwidth doubled

Cells arranged in two (independent) banks

Consecutive words stored in different banks (interleaving)

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Memory Modules
Single In-line Memory Module (SIMM)

30-pin (8-bits)

1 MB to 16 MB

72-pin (32-bit)

1MB to 64 MB

Dual In-line Memory Module (DIMM)

168-pin (64-bits)

8 MB to 4 GB

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Memory Module Organization

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Read-Only Memories
ROM

Cell (not) connected to ground stores a (1) 0

Programmable using fused connection (UV) Erasable via programmable transistor Electrically erasable
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PROM

EPROM

EEPROM

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Flash Memory
Flash Cell

Single transistor controlled by trapped charge Read single cell, Write block of cells
Flash chips mounted on small card Standard interface Emulate hard disk drives
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Flash Cards

Flash Drives

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Memory Hierarchy
Processor Registers

Increasing Size

Primary Cache

Increasing Speed

Increasing Cost

Secondary Cache

Main Memory

Secondary Memory
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Questions?

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