Design of storage elements and the associated address Main System Components: Power Supply Reset logic System oscillator Chipset Peripherals: Interrupt- and DMA Controller, Clock generator Real Time Clock Interfaces: Parallel and serial, Standards (RS232, USB, ...)
Parallel Port The Centronics printer interface transmits eight bits of data at a time to an external device, normally a printer. A 25-pin D-type connector is used to connect to the PC and a 36-pin Centronics interface connector normally connects to the printer. This interface is not normally used for other types of interfacing as the standard interface only transmits data over the data lines in one direction, that is, from the PC to the external device. Some interface devices overcome this problem by using four of the input handshaking lines to input data and then multiplexing using an output handshaking line to multiplex them to produce eight output bits. As technology has improved there is a great need for a bidirectional parallel port to connect to devices such as tape backup drives, CD-ROMs, and so on. The Centronics interface unfortunately lacks speed (150 kbps), has limited length of lines (2m) and very few computer manufacturers comply with an electrical standard. Parallel Port To allow higher-speeds the EPP (enhanced parallel port) and ECP (extended capabilities port protocol) modes have been developed. They allow high-speed data transfer using automatic hardware handshaking. With this standard all parallel ports use a bidirectional link in either a compatible, nibble or byte mode. These modes are relatively slow as the software must monitor the handshaking lines (up to 100 kbps). These modes use hardware to assist in the data transfer. For example, in EPP mode, a byte of data can be transferred to the peripheral by a simple OUT instruction. The I/O controller handles all the handshaking and data transfer to the peripheral. Centronics parallel interface Centronics parallel interface showing pin numbers on PC connector Data handshaking The main handshaking lines are nACK , BUSY and nSTROBE. 1. Initially the computer places the data on the data bus, 2. then it sets the nSTROBE line low to inform the external device that the data on the data bus is valid. 3. When the external device has read the data, it sets the nACK lines low to acknowledge that it has read the data. 4. The PC then waits for the printer to set the BUSY line inactive, that is, low. Accessing the Parallel Interface The parallel interface can be accessed either by direct reads to and writes from the I/O memory addresses or from a program which uses the BIOS printer interrupt. This interrupt allows a program either to get the status of the printer or to write a character to it. Handshake Data handshaking with the Centronics parallel printer interface Signal definitions Signal In/out Description STROBE Out Indicates that valid data is on the data lines (active low) AUTO FEED Out Instructs the printer to insert a line feed for every carriage return (active low) SELECT INPUT Out Indicates to the printer that it is selected (active low) INIT Out Resets the printer ACK In Indicate that the last character was received (active low) BUSY In Indicates that the printer is busy and thus cannot accept data OUT OF PAPER In Out of paper SELECT In Indicates that the printer is on line and connected ERROR In Indicates that an error exists (active low) I/O addressing Addresses The printer port has three I/O addresses assigned for the data, status and control ports. These addresses are normally assigned to: Printer Data register Status register Control register LPT1 378H 379H 37AH LPT2 278H 279H 27AH Output lines The data port register links to the output lines. Writing a 1 to the bit position in the port sets the output high, while a 0 sets the corresponding output line to a low. The output data lines are each capable of sourcing 2.6mA and sinking 24mA; it is thus essential that the external device does not try to pull these lines to ground. The control port also contains five output lines, of which the lower four bits are STROBE , AUTO FEED , INIT and SELECT INPUT . These lines can be used as either control lines or as data outputs. With the data line, a 1 in the register gives an output high, while the lines in the control port have inverted logic. Thus a 1 to a bit in the register causes an output low. The value for the control output lines must be invert, so that the STROBE line will be set to a 1 so that it will be output as a LOW. Output lines The setting of the output value is slightly confusing as the output is the inverse of the logical setting (that is, a 1 sets the output low). An alternative method is to exclusive-OR (EX-OR) the output value with $B which will invert the 1st, 2nd and 4th least significant bits ( SELECT INPUT =0, AUTO FEED =1, and STROBE =0), while leaving the 3 rd
least significant bit (INIT) untouched. If the 5th bit on the control register (IRQ enable) is written as 1 then the output on this line will go from a high to a low which will cause the processor to be interrupted. The control lines Are driven by open collector drivers pulled to +5Vdc through 4.7 k resistors. Each can sink approximately 7mA and maintain 0.8V down-level. Output lines Output lines Inverted Inverted Inverted 7 0 3 4 7 0 IRQ Inputs There are five inputs from the parallel port: BUSY, nACK , PE, SELECT and nERROR. The status of these lines can be found by simply reading the upper 5 bits of the status register. Unfortunately, the BUSY line has an inverted status. Thus when a LOW is present on BUSY, the bit will actually be read as a 1. For example a program might read the bits from the status register, invert the BUSY bit and then shift the bits three places to the right so that the five inputs bit are in the five least significant bits. Input lines Input lines Inverted 7 0 EPP - enhanced parallel port EPP mode defines a standard bidirectional communications mode is used by many peripherals, such as CD-ROMs, tape drives, external hard disks and so on. The EPP protocol provides four types of data transfer cycles: 1. Data read and write cycles These involve transfers between the host and the peripheral. 2. Address read and write cycles These pass address, channel, or command and control information. EPP - Operation The WRITE occurs automatically when the host writes data to the output lines. The data write cycle has the following sequence: 1. Program executes an I/O write cycle to the base address port + 4 (EPP data port). Then the following occur with hardware: 2. The WRITE line is set LOW, which puts the data on the data bus. 3. The DATASTB is then set LOW. 4. The host waits for peripheral to set the WAIT line HIGH. 5. The DATASTB and WRITE are then HIGH and the cycle ends. The important parameter is that it takes just one memory-mapped I/O operation to transfer data. This gives transfer rates of up to 2 million bytes per second. Although it is not as fast as a peripheral transferring over the ISA, it has the advantage that the peripheral can transfer data at a rate that is determined by the peripheral. EPP mode signals Compatibility signal name EPP mode name In/out Description
STROBE WRITE Out A LOW for a write operation while a HIGH indicates a read operation. AUTO FEED DATASTB Out Indicates a data read or write operation. SELECT INPUT ADDRSTROBE Out Indicates an address read or write operation. INIT RESET Out Peripheral reset when LOW. ACK INTR In Peripheral sets this line LOW when it wishes to interrupt to the host. BUSY WAIT In When it is set LOW it indicates that it is valid to start a cycle, else if it is HIGH then it is valid to end the cycle. PE User defined In Can be set by each peripheral. SELECT User defined In Can be set by each peripheral. ERROR User defined In Can be set by each peripheral. D0D7 AD0AD7 In/out Bidirectional address and data lines. EPP registers Several extra ports are defined, these are the EPP address register and EPP data register. The EPP address register has an offset of three bytes from the base address and the EPP data register is offset by four bytes. EPP register definitions Port Name I/O address Read/ write Description Data register BASE_AD W Status register BASE_AD +1 R Control register BASE_AD +2 W EPP address port BASE_AD+3 R/W Generates EPP address read or write cycle EPP data port BASE_AD+4 R/W Generates EPP data read or write cycle ECP - extended capability port The ECP protocol was proposed by HP and Microsoft as an advanced mode for communication with printer and scanner type peripherals. It provides a high performance bidirectional data transfer between a host and a peripheral. The standard provides for two cycle types in both forward and reverse directions: 1. Data cycles. 2. Command cycles which can either be a run length count or a channel address. ECP advantages over the EPP standard Standard addresses ECP has standard register addresses (addresses from 0778h to 077Ah have been defined for the extra functionality of ECP). Run length encoding (RLE) RLE allows for compression. It allows high compression rates when there is a great deal of repetitive information in a file (typically with graphics files). A repetitive sequence is identified by a count followed by the repeated byte. FIFOs for both the forward and reverse channels. DMA as well as programmed I/O for the host register interface. Channel addressing This allows multiple logical devices to be located within a single physical device. ECP mode signals Compatibility signal name ECP mode name In/out Description STROBE HostClk I Transfers data or address information in the forward direction (along with PeriphAck). AUTO FEED HostAck O Command/Data status in the forward direction. Data transfer in reverse direction (along with PeriphClk). SELECT INPUT 1284Active O Set high when host is in a 1284 transfer mode. INIT ReverseRequest O A low puts channnel in reverse direction. ACK PeriphClk I Transfer data in the reverse direction (along with HostAck). BUSY PeriphAck I Transfer data or command information (along with HostClk). PE nAckReverse I Acknowledgement to nReverseRequest SELECT Xflag I Extensibility flag. ERROR nPeriphRequest I Set low by peripheral to indicate that reverse data is available. D0D7 Data[8:1] I/O Data lines. USB USB (Universal Serial Bus) allows for the connection of medium bandwidth peripherals such as keyboards, mice, digital speakers/ microphones tablets, Game controllers modems, Scanners/ printers/ monitors telephones, HDD and CD-ROM drives, printers and other low to moderate speed external peripherals in a tiered-star topology. USB - basic specification is: Isochronous (continuous) transfers which supports audio and video. With isochronous data transfers, devices transmit and receive data in a guaranteed and predictable fashion. USB also supports non-isochronous devices (the highest priority), and both isochronous and non- isochronous can exist at the same time. Standardized industry-wide plug-and-play specification, cables and connections. Multiple-tiered hubs with almost unlimited expansion (with up to 127 physical devices), and concurrent operations. 12Mbps transfer rate and different packet sizes. It supports many device bandwidth requirements from a few kbps to 12Mbps. Wide range of device data rates by accommodating packet buffer size and latencies. A hot-plug capability which allows peripherals to be connected without powering down the computer. Dynamically attachable and reconfigurable peripherals. Enhanced power management with system hibernation and sleep modes. Self-identifying peripherals, automatic mapping of function to driver and configuration. Support for compound devices which have multiple functions. Flow control for buffer handling built into protocol. Error handling/fault recovery mechanism. Support for identification of faulty devices. Simple protocol to implement and integrate. USB - features USB is a balanced bus architecture which hides the complexity of the operation from the devices connected to the bus. The USB host controller controls system bandwidth. Each device is assigned a default address when the USB device is first powered or reset. Hubs and functions are assigned a unique device address by USB software. Physical USB connection USB uses a four-wire cable to connect to devices. One pair of the twisted-pair lines gives the differential data lines (D+ and D), the other two gives a 5V and a GND supply rail. Data transfer rate is up to 12Mbps, with a 1.5Mbps subchannel for low-data-rate devices (such as a mouse). A single unit can connect directly to the PC, a hub is required when more than one device is connected. Each peripheral can extend up to 5m from each hub connection, maximum of 127 different devices to a single PC. USB - Bus protocol Each bus transaction involves the transmission of up to three packets. These are Token packet transmission on a scheduled basis, the host controller sends a USB packet which describes the type and direction of a transaction, the USB device address and endpoint number. The addressed USB device selects itself by decoding the appropriate address fields. Data packet transmission the source of the transaction then sends a data packet, or indicates it has no data to transfer. Handshake packet transmission destination device responds with a handshake packet to indicate whether the transfer was successful.