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PROJECT PHASE-II

Presented by, Guided by,
Velumani.V T.Kowsalya M.E.,(Ph.d)
(714512419013) (Associate Professor / ECE)

United Institute of Technology, Coimbatore.
ME-VLSI DESIGN



OBJECTIVE
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Reduced partial products
Reduced Computation cycles
Critical paths reduced
Reduces power and Delay





LITERATURE SURVEY
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METHOD/Authors


OPERATING MODE

CYCLES
Gnanasekaran [12] UNSIGNED 2n
Gnanasekaran [12] SIGNED 2n
Aggoun [14] UNSIGNED 2n
Pekmestzi [15] UNSIGNED 2n
Proposed
Multiplier
UNSIGNED
/SIGNED

n

ABSTRACT
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Conventional serial-serial multipliers 2n cycles n*n
multiplications
Proposed serial-serial multipliers n cycles n*n
multiplications
achieves a high bit sampling rate by replacing
conventional full adders and 5:3 counters with
asynchronous 1s counters so that the critical path is
limited to only an AND gate and a D flip-flop
Proposed hybrid column compressed multiplier
consists of a serial-serial data accumulation unit and a
parallel carry save adder (CSA) array
INTRODUCTION
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Good multiplier design tradeoff between speed
and power consumption
generation of partial products (PPs)
reduction of PPs (CSA)
final carry-propagation addition



IMPORTANCE OF SERIAL-SERIAL
MULTIPLIER
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CONT
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CSAS SERIAL-PARALLEL
MULTIPLIERS
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UNSIGNED
MULTIPLIER
SIGNED MULTIPLIER
PROPOSED ARCHITECTURE
(UNSIGNED MULTIPLICATION)
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PROPOSED ARCHITECTURE
(SIGNED MULTIPLICATION)
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PARTIAL PRODUCT FORMATION
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Conventional
Multiplier
Proposed
Multiplier
IMPLEMENTATION OF EXISTING
UNSIGNED MULTIPLIER
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OUTPUT WAVEFORM FOR
EXISTING UNSIGNED MULTIPLIER
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IMPLEMENTATION OF EXISTING
SIGNED MULTIPLIER
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OUTPUT WAVEFORM FOR
EXISTING SIGNED MULTIPLIER
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IMPLEMENTATION OF PROPOSED
UNSIGNED MULTIPLIER
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OUTPUT WAVEFORM FOR
EXISTING UNSIGNED MULTIPLIER
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IMPLEMENTATION OF PROPOSED
SIGNED MULTIPLIER
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OUTPUT WAVEFORM FOR
EXISTING SIGNED MULTIPLIER
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Performance Analysis for Unsigned
Multipliers
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Parameter

Active devices

Power
(w)

Delay
(ns)


PDP
(nw/s)

EDP (aj/s)

Proposed 8*8
Multiplier


2716

0.457

1.052

0.479

0.503

Existing 8*8
Multiplier


816

0.160

4.39

0.690

3.032
Chart Analysis for Unsigned Multipliers
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Performance Analysis for Signed
Multipliers
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Parameter

Active
Devices


Power
(w)

Delay
(ns)

PDP
(nw/s)

EDP
( aj/s)

Proposed 8 x 8
Multiplier


4046

0.0126

2.01

0.025

0.050

Existing 8 x 8
Multiplier


837

0.168

4.4

0.704
'
3.097
Performance Analysis for Signed
Multipliers
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Clock cycles comparison result for
Proposed & Existing multipliers
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Multiplier

8 x 8 Signed Multiplication

8 x 8 Unsigned Multiplication

Proposed Multiplier

8 Cycles

8 Cycles

Existing Multiplier


16 Cycles

16 Cycles
TOOL USED
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TANNER EDA TOOL V13.0

CONCLUSION & FUTURE
ENCHANCEMENT
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PP obtained in 8 Computation Cycles (n x n Multiplication)
Delay reduced
Suitable for Complex Soc & Advance FPGA
In future RCA is replaced with KSA, Power will be
reduced
REFERENCES
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[1] Manas Ranjan Meher, Ching Chuen Jong, and Chip-Hong Chang, A High
Bit Rate Serial- Serial Multiplier with On-the-Fly Accumulation by
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[3] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. New
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multiplication and squaring over GF(2
m
), IEEE Trans. Comput., vol. 58, no.
10, pp. 13321345, Oct. 2009.

CONT..
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CONT.,
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[13] P. Ienne and M. A Viredaz, Bit-serial multipliers and squarers, IEEE Trans.
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2000, pp. 585588.
[15] K. Z. Pekmestzi, P. Kalivas, and N. Moshopoulos, Long unsigned number
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IEEE Trans. Comput., vol. C-32, no. 9, pp. 878880, 1983.
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THANK YOU
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