Simple tutorial

http://www.altera.com/products/software/qu
artus-ii/web-edition/qts-we-index.html
Download software button
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Choose OS, Quartus II and Modelsim, At least
1 device Download
Install Quartus II Modelsim
Add device to Quartus II
Start Quartus II Tools Install Devices Follow
the wizard for the downloaded device file (.qzd)
Start Quartus II software
File New Project Wizard
Next
Page 1/5: Choose directory, project name (no empty
spaces). Next.
Page 2/5: Next (unless you have existing files to use)
Page 3/5: Choose any device. E.g. Cyclone II,
EP2C35F672C6. Next
(Choosing the correct device is important when you are
using FPGA board. The device name is normally written on
the FPGA itself.
Page 4/5: Next.
(you can specify the third-party tools if you need to)
Page 5/5: Finish.
Design entry using schematic
File New
Choose Block Diagram/Schematic File OK
Draw the circuit
Double click on the drawing area
Choose components under libraries (or search)
Input, Output, Gates, Etc
To copy, hold control click and drag item to copy
To connect, click on the end of connection and drag
Rename by double clicking the name
Synthesizing
Processing Start Compilation
Create VHDL code for schematic
File Create/Update Create HDL Design File
from Current File
Choose VHDL
.vhd file is created in the project directory

Start ModelSim
File New Project
Choose project name and location OK
Add existing file (Project Add to project
Existing file
Choose the .vhd file created earlier
OK
Compiling the files
Compile Compile all
Library tab expand work
Simulating a design
Double click design object (entity etc) in library tab,
or
Right click the name and select simulate, or
Simulate Start Simulation Select the design
and options.
View Wave or type view wave in the command
Right click project name in sim tab Add to
Wave All items in region
Assign input signals
Use clock (right click set clock), or
Force command (force <input name> <value> <time-
stop>). Repeat for all inputs and time.

Field Programmable Gate Array
A semiconductor device that can be
programmed multiple times to implement
digital circuits within it.
Contains I/O* cells, programmable logic
blocks and reconfigurable interconnects that
allows the blocks to be wired together.

*I/O = Input/output
To define FPGAs behavior, HDL is normally used.
Two popular HDLs are:
Verilog
VHDL (Very-High-Speed Integrated Circuits HDL)
Within a VHDL program:
Library Import
Entity Definition*
Architecture Definition*
*-Must have definitions
Describes the ports or interface of the digital
system.
Ports can be in, out or inout (both) with different
signal types:
bit
std_logic
std_logic_vector
Example of entity declaration for ANDGATE:
--this is the entity
entity ANDGATE is
port (A : in bit;
B : in bit;
Z : out bit);
end entity ANDGATE;
Comment in VHDL
starts with --
Definition of new entity
(ANDGATE)
End of new entity
definition
}
Describes the interface
of device:
-A and B are inputs (in)
with signal type std_logic
-Z is output (out) with
signal type std_logic
Describe how the design operates.
<== and semi colons are required
-- this is the architecture
architecture myArch of ANDGATE is
begin
Z <= A and B;
end architecture myArch;