Liserre Lecture 7-1

Grid synchronization for power converters
Marco Liserre liserre@ieee.org

Grid synchronization for power
converters
Marco Liserre

liserre@poliba.it

Grid requirements for DG inverters
PLL Basics, PLL in power systems
Design of PLL
PLL for single-phase systems
Methods to create the orthogonal component
Methods using adaptive filters
PLL for three-phase systems
Conclusions
Reference papers
Outline
Grid
Distrurbances
Thomsen,1999; CIGRE WG14-31, 1999
Grid disturbances are not
at all a new issue, and
the utilities are aware of
them. However, they
have to take a new look
because of the rapidly
changing customers
needs and the nature of
loads (CIGRE WG14-31,
1999)
Grid requirements for DG inverters
The following conditions should be met, with voltages in RMS and
measured at the point of utility connection.
When the utility frequency is outside the range of +/- 1 Hz the inverter
should cease to energize the utility line within 0.2 seconds.
The PV system shall have an average lagging power factor greater
than 0,9 when the output is greater than 50% rated.
Thus the grid voltage and frequency should be
estimated and monitored fast and accurate enough in
order to cope with the standard
Grid synchronization requirements
A good synchronization of the current with the grid voltage is
necessary as:

the standards require a high power factor (> 0.9)
a clean reference for the current is necesarry in order to cope with the
harmonic requirements of grid standards and codes
grid connection transients needs to be minimized in order not to trip the
inverter

Distributed Generation systems of higher power have also requirements in
terms of voltage support or reactive power injection capability and of
frequency support or active power droop

Micro-grid distributed generation systems have wider range of voltage and
frequency and the estimated grid voltage parameters are often involved in
control loops
Grid synchronization options and challenges
There are two basical synchronization methods:
Filtered Zero Cross Detection (ZCD)
PLL

Single-phase systems:
The classical solution for single-phase systems was Filtered ZCD as for the PLL
two orthogonal voltages are required.
The trend now is to use the PLL technique also by creating virtual
orthogonal components using different techniques!

Three-phase systems:
Three-phase PLL should deal with unbalnace hence with negative sequence
Moreover in three-phase systems dynamics would be better if synchronizing
to all three phase voltages, i.e. based on space vectors rather then on a scalar
voltage
Zero Cross Detection (ZCD) circuits
Resistive feedback hysteresis
circuit
Dual point interpolation circuit
Dynamic hysteresis comparator
circuit
Source: R.W. Wall, Simple methods for detecting
zero crossing, IEEE IECON03, pp. 2477-2481
Filtered Zero Cross Detection (ZCD) based
monitoring and synchronization
v
2
1
x dt
T

}
1
2 t
e
}
u
T
+
f
V
sin
-
I
I
-
OV/UV
OF/UF
TRIP
Filter
max
V
min
V
min
f
max
f
RMS CALC
2
x
t
RST
k
u
fil
v
ZCD
max
V
min
V
min
f
max
f
V
f
v
fil
v
u
Filtering introduces delay. There are digital predictive FIR filters without
delay bu with high complexity (very high order!)
The RMS voltage and frequency are calculated once in a period poor
detection of changes (sags, dips, etc.)
-200
-100
0
100
200
v

[
V
]
Basic idea of synchronization based on a phase-locked loop:

Phase-locked technology is broadly used in military, aerospace, consumer electronics systems
where some kind of feedback is used to synchronize some local periodic event with some
recognizable external event
Many biological processes are synchronized to environmental events. Actually, most of us
schedule our daily activities phase-locking timing information supplied by a clock.
A grid connected power converter should phase-lock its internal oscillator to the grid voltage
(or current), i.e., an amplitude and phase coherent internal signal should be generated.

Event based synchronization
(simple, discontinuous, )
in
u
v
Phase-locked synchronization
(continuous, predictive,)
PLL basis
Basic blocks:

Phase Detector (PD). This block generates an output signal proportional to the phase
difference between its two input signals. Depending on the type of PD, high frequency ac
components appear together the dc phase difference signal.

Loop Filter (LF). This block exhibits low pass characteristic and filters out the high frequency ac
components from the PD output. Typically this is a 1-st order LPF or PI controller.

Voltage Controlled Oscillator (VCO). This block generates at its output an ac signal whose
frequency varies respect a central frequency as a function of the input voltage.
Phase
Detector
Loop
Filter
Voltage
Controlled
Oscillator
f
v v
v
'
d
v
PLL basis
PLL in power systems
v
a
v
b
T
1
T
3
E
v
dc
T
5
v
c

i
a
T
4
T
6
T
2
L
S
+
-
L
L
R
L
In 1968 Ainsworth proposed to use a voltage
controlled oscillator (VCO) inside the control loop
of a High Voltage Direct Current (HVDC)
transmission system to deal with the novel, at that
time, harmonic instability problem.

Subsequently, analog phase locked
loops (PLL) were proposed to be used as
measurement blocks, which provide frequency
adaptation in motor drives.
Phase Locked Loop tuning
cos( ) x
p i
k k +
}
}
o
k
d
k
e
c
e
e
s
d
v
( ) sin
in in
A t e +
PD LF
VCO
c
( )
sin
in in in
v A t = +
( )
cos
VCO c out
v t = +
Reference:
VCO output:
PD/Mixer output: ( ) ( ) ( ) ( ) ( ) ( )
sin cos sin sin
2
d
d d in in c out in c in out in c in out
Ak
v Ak t t t t ( = + + = e +e + + + e e +

VCO angle: c o e out o e
t k s dt k s dt = e + =
} }
if , then ,
S
m
a
l
l

s
i
g
n
a
l

a
n
a
l
y
s
i
s
:

in
c
= e
( ) ( )
sin 2 sin
2
d
d in in out in out
Ak
v t ~ e + + + (

in out
~ ( ) ( ) ( )
sin 2
2
d
d in in in out
Ak
v t
(
~ e + +

The average value is
( )
2
d
d in out
Ak
v ~
( ) ( ) sin
in out in out
~
if , then ,
Phase Locked Loop tuning
2
( )
( )
( )
p
p
out i
p
in
p
i
k
k s
s T
H s
k
s
s k s
T
= =
+ +
;
2
p i p
n
i
k T k
T
e = =
1.8
r
n
t =
e
2
9.2
;
2.3
s
p i
s
t
k T
t

= =
1
1
p
i
k
T s
| |
+
|
\ .
e
s
d
v
PD LF - H
PI VCO
c
in
out
o
k
m
k
1
s
1 1
o m
k k = =
assuming
that can be written as
2
2 2
( ) 2
( )
( ) 2
out n n
in n n
s s
H s
s s s
,e + e
= =
+ ,e + e
with
4.6
s
n
t =
e
The PLL can be tuned as function of the
damping and of the settling time
then
The hold range Ae
H
is the frequency range at which a PLL is able to maintain lock statically.
Key parameters of the PLL
(0)
H o m
k k LF Ae =
The lock range Ae
L
is the frequency range within which a PLL locks within one-single beat
note between the reference frequency and the output frequency.
For the PI, LF(0)= and the hold range is only limited by the frequency range of the VCO
2 2
p
L n
i
k
T
Ae ~ e ~
Pull-in time:
2
L
n
T
t
~
e
The pull-in range Ae
P
is the frequency range at which a PLL will always became locked, but
the process can become rather slow. For the PI loop filter this range trends to infinite.
0 0.5 1 1.5 2 2.5
0
100
200
300
400
t [s]
e
'

[
r
a
d
/
s
]
0 0.5 1 1.5 2 2.5
0
2
4
6
8
t [s]
u
'

[
r
a
d
]
Lock-in time:
2 2
3
16
in
P
n
T
Ae t
~
e
Phase Locked Loop: the need of the orthogonal
component
1
1
p
i
K
sT
| |
+
|
\ .
X
X
cos
sin
s
1
in e
( ) Vsin -
in out

( ) Vsin
in in
t e +
( ) Vcos
in in
t e +
in out
t e +
+
+
+
-
To eliminate the 2 harmonic oscillation from
( ) ( ) sin 2 sin
2
d
in in out in out
Ak
t e + + + (

and obtain it should be considered that ( ) sin
2
d
in out
Ak
(

( )
sin - sin cos cos sin
in out in out in out
=
Park transformation in the PD
cos( ) sin( )
sin( ) cos( )
d out out
q out out
v v
v v
o
|
( ( (
=
( ( (

Park transformation:
sin( )
cos( )
in
in
v
V
v
o
|
( (
=
( (

( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
( )
( )
sin cos cos sin sin
sin sin cos cos cos
d in out in out in out
q in out in out in out
v
V V
v
( ( (
= =
( ( (

Assuming e
in
=e
out
:
( )
( )
sin
cos
d in out
q in out
v
V
v
u u ( (
=
( (
u u

1
1
p
i
k
T s
| |
+
|
\ .
f
v
d
v
LF VCO
1
s
c
e
q
v
o|
dq
v
o
v
|
out
out
PD
in
v Quadrature
Signal
Generator
v
o
v
|
q
v
d
v
|
d
q
in
out
sin( )
in
v V
o
=
v
o
Park transformation in the PD
0
0
in
t =
=
o
|
d
q
v
0
2
out
t =
t
=
sin( ) ; 0
in q
v V v
o
= =
0
0
in
t =
=
o
|
d
q
v
0
0
out
t=
=
sin( ) ; 0
in d
v V v
o
= =
1
1
p
i
k
T s
| |
+
|
\ .
f
v
d
v
LF VCO
1
s
c
e
o|
dq
v
o
v
|
out in
=
out
PD
in
v Quadrature
Signal
Generator
q
v v =
1
1
p
i
k
T s
| |
+
|
\ .
f
v
LF VCO
1
s
c
e
q
v
o|
dq
v
o
v
|
2
out in
t
=
out
PD
in
v Quadrature
Signal
Generator
d
v v =
PI on v
d
PI on v
q
From here on, it will be considered:
and PI on v
q,
, i.e.,
Therefore:
( )
sin
in in
v v V
o
= =
0
q
v =
and
out in d
v v V = = =
Transport Delay T/4
The transport delay block is easily implemented through the use of a first-in-first-out
(FIFO) buffer, with size set to one fourth the number of samples contained in one
cycle of the fundamental frequency.
This method works fine for fixed grid frequency. If the grid frequency is changing
with for ex +/-1 Hz, then the PLL will produce an error
If input voltage consists of several frequency components, orthogonal signals
generation will produce errors because each of the components should be delayed
one fourth of its fundamental period.
1
1
p
i
k
T s
| |
+
|
\ .
e
s
d
v
LF VCO
1
s
c
e
q
v
o|
dq
Delay
T/4
v
o
v
|
'
u
u
PD
in
v
in
v
Inverse Park Transformation
A single phase voltage (v
o
) and an internally generated signal (v
|
) are used as inputs to a Park
transformation block (-dq). The d axis output of the Park transformation is used in a control loop to
obtain phase and frequency information of the input signal.
v
|
is obtained through the use of an inverse Park transformation, where the inputs are the d and q-
axis outputs of the Park transformation (dq-). fed through first-order low pass filters.
Although the algorithm of the PLL based on the inverse Park transformation is easily implemented,
requiring only an inverse Park and two first-order low-pass filters
1
1
p
i
k
T s
| |
+
|
\ .
e
s
d
v
LF VCO
1
s
c
e
q
v
o|
dq
v
o
v
|
'
u
u
PD
in
v
in
v
o|
dq
LPF
LPF
d
v
q
v
v
|
'
v
o
'
}
k
SOGI
v v'
q v'
}
e'
e'
Second Order Generalized Integrator
2 2
( ) ( )
d s
S s s
f s
e
e
'
= =
' +
}
SOGI
d
q
}
e'
e'
f
2
2 2
( ) ( )
q
T s s
f s
e
e
'
= =
' +
2 2
( ) ( )
v k s
D s s
v s k s
e
e e
' '
= =
' ' + +
2
2 2
( ) ( )
qv k
Q s s
v s k s
e
e e
' '
= =
' ' + +
-60
-40
-20
0
20
M
a
g
n
i
t
u
d
e

(
d
B
)
10
-1
10
0
10
1
10
2
10
3
10
4
-90
-45
0
45
90
P
h
a
s
e

(
d
e
g
)
Frequency (Hz)
k=0.1
k=1
k=4
-60
-40
-20
0
20
M
a
g
n
i
t
u
d
e

(
d
B
)
10
-1
10
0
10
1
10
2
10
3
10
4
-180
-135
-90
-45
0
P
h
a
s
e

(
d
e
g
)
Frequency (Hz)
k=0.1
k=1
k=4
( ) D e
( ) Q e
}
k
}
k
out
v
v
c
in
v
cos
sin
' u
' u
OSCILLATOR
Adaptive Notch Filter (ANF)
2 2
2 2
( ) ( )
out
in
v s
ANF s s
v s ks
e
e
' +
= =
' + +
v
out
=0 when:

v
out
can not be directly used as
PD in the PLL
t ' = + e u e o o
v
out
=0 when:

v
out
can be used as PD in the
PLL
in
t ' = + u e u
}
k
out
v
v
c
in
v
cos
' u
OSCILLATOR
( )
cos
in in
v A t e u = +
ANF-based PLL
PD
k
v
c
cos
in
v
' u
e
s
LF
VCO
1
s
c
e
Adaptive Notch Filter
d
v
c
k
1
s
Very sensible to frequency variation
ANF+PLL EPLL
More robust
Faster dynamic response
PD
k
v
c
cos
in
v
' u
1
1
p
i
k
T s
| |
+
|
\ .
e
s
LF VCO
1
s
c
e
sin
Adaptive Notch Filter
d
v
Conventional PLL structure
1
s
Combination of an ANF with a
conventional PLL gives rise to the
Enhanced PLL (EPLL)
d
v
}
k
v v'
PI
}
cos
e'
u'
ju
u
v
c ( )
V
e
'
ABPF
ff
e
v v
sin
VCO
LF
PD
Enhanced PLL (EPLL)
Original structure of the EPLL
90
K
p
K
i

sin
+ +
+
+
+
-
y
A
BPAF LP VCO
v e
1
s
1
s
1
s
2 2
( ) ( )
v k s
D s s
v s k s
e
e e
' '
= =
' ' + +
SOGI-PLL
2 2
( ) 1 ( ) ( )
v ks
ABPF s ANF s s
v s ks e
'
= = =
' + +
Adaptive band-pass filter:
Damping factor is a function of
the detected frequency value
Second order generalized integrator follower:
If e can change, SOGI follower can be seen
as an adaptive band-pass filter with damping
factor set by k and unitary gain
As in the EPLL, a standard PLL can be
used to detect grid frequency and angle
ju is 90-leading v when the PLL is
synchronized in steady state
ju=-qu and qu qv
It seems intuitive to use -qu (instead ju) as
the feedback signal for the PD of the PLL
v
c
VCO
}
k
v v'
}
qv'
PI
}
e'
u'
ju
ff
e
sin
LF
e'
SOGI
v
c
PD
Conventional PLL structure
SOGI-based Frequency Locked Loop (SOGI-FLL)
v
c
}
k
v v'
}
qv'
e'
SOGI
1
}
ff
e
v
c
qv'
FLL
Does not need any trigonometric function since
neither synchronous reference frame nor voltage
controlled oscillator are used in its algorithm.
Is frequency-adaptive by using a FLL and not a
PLL.
Is highly robust in front of transient events
since grid frequency is more stable than voltage
phase-angle.
Attenuates high-order harmonics of the grid
voltage.
Entails light computational burden, using only
five integrators for detection of both sequence
components.
Distorted and unbalanced voltage vector
Three-phase grid synchronization
u t e
t e
1 +
S
V
1
S
V
S
V
o
|
a
b
c
1
S
V
1 +
S
V
1 1 +
S S
V V
1 1 +
+
S S
V V
1 2 1 2 1 1 1
( ) ( ) 2 cos( 2 )
S S S S S
V V V V t e |
+ +
= + + + v
1 1
1
1 1 1
sin( 2 )
tan
cos( 2 )
S
S S
V t
t
V V t
e |
u e
e |

+
| | +
= +
|
+ +
\ .
o
|
a
b
c
S
V
1 +
S
V
5
S
V
5
S
V
1 +
S
V
( ) ( )
( )
| |
v
S S S
n
S S
n
V V V V n t = + +
+ + 1
2 2
1
2 1 cos e
( )
| |
( )
| |
u e
e
e
= +

+
+
t
V n t
V V n t
S
n
S S
n
tan
sin
cos
1
1
1
1
Neither constant amplitude nor
rotation speed
Characterization of voltage dips
0 0.02 0.04 0.06 0.08 0.1
-1.5
-1
-0.5
0
0.5
1
1.5
V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995
t [s]
v
a
b
c

[
p
u
]
0 0.02 0.04 0.06 0.08 0.1
-1.5
-1
-0.5
0
0.5
1
1.5
V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995
t [s]
v
o
|

[
p
u
]
-1.5 -1 -0.5 0 0.5 1 1.5
-1.5
-1
-0.5
0
0.5
1
1.5
V=0.5<-20 ;F=0.75<-40 V+=0.61589<-32.0197 ;V-=0.16411<108.5995
v
o
[pu]
v
|

[
p
u
]
3 1
2 2
3 1
2 2
Type C
Sa
Sb
Sb
V F
V F jV
V F jV
=
=
= +
3 1
2 2
3 1
2 2
Type D
Sa
Sb
Sb
V V
V V jF
V V jF
=
=
= +
( )
( )
1
1
2
1
1
2
Type C
S
S
V V F
V V F
+
= +
=
( )
( )
1
1
2
1
1
2
Type D
S
S
V V F
V V F
+
= +
=
Phase-voltages from
characteristic parameters
Sequence components from
characteristic parameters
Three-phase Synchronous Reference Frame PLL
PI
s
1
Sa
v
Sb
v
Sc
v
| |
dq
T
Sd
v
Sq
v
e

u
Sd S
v v
-150
-100
-50
0
50
100
150
0
1
2
3
4
5
6
7
0 25 50 75 100
-50
0
50
100
150
t [ms]
-150
-100
-50
0
50
100
150
0
1
2
3
4
5
6
7
0 25 50 75 100
-50
0
50
100
150
t [ms]
Balanced
voltage
Unbalanced
voltage
S
v
S
v
t u e =
t e
u
Sd S
v = v
0
Sq
v =
Sd S
v ~ v
0
Sq
v ~
1
1 1
1
( )

cos( ) cos( )

sin( ) sin( )
Sd
S S S
dq
Sq
v t t
V V
v
t t
e u e | u
e u e | u
( (
+ (
= = +
( (
(
+ ( (

v
-150
-100
-50
0
50
100
150
0
1
2
3
4
5
6
7
-50
0
50
100
150
The SRF is not able to track instantaneous evolution
of the voltage vector when the PLL bandwidth is low
S
v
t u e ~
Sd
v
Sq
v
0 25 50 75 100
-150
-100
-50
0
50
100
150
t [ms]
t e
1
S
+
v
1 1
( )
1 cos( 2 )
v
' sin( 2 )
S S S
dq
t
V V
t t
e
e u e
+
( (
~ +
( (

' t u e ~ Near of synchronization:
sin( ') ' t t e u e u ~ cos( ') 1 t e u ~ ' 2 t t e u e ~
PI
s
1
Sa
v
Sb
v
Sc
v
| |
dq
T
Sd
v
Sq
v
e

u
Sd S
v v
| |
1
1 1
1
sin(2 ) ' '
S
Sq S S
S
V
v V t t V
V
e e u u
+ +
+
(
~ =
(

1
1
sin(2 )
S
S
V
t t
V
e e
+
=
u
i
p
k
k
s
+
e
1
s
1
S
V
+
c
*
1 +
Sq
v
2
2 2
2
( ) ( )
2
c c
c c
s
P s s
s s
u e e
e e
+
= =
+ +
1
c S i
V k e
+
=
1
2
p
S
i
k
V
k
+
=
-150
-100
-50
0
50
100
150
Setting a low PLL bandwidth and using a low-pass filter it is possible to obtain a
reasonable approximation of the positive sequence voltage but the dynamic is too slow.
S
v
0
1
2
3
4
5
6
7
-50
0
50
100
150
Sq
v
Sd
v
0 25 50 75 100
-150
-100
-50
0
50
100
150
t [ms]
1
S
+
v
PI
s
1
Sa
v
Sb
v
Sc
v
| |
dq
T
Sd
v
Sq
v
e

u
Sd S
v v
Repetitive
controller
Advanced filtering strategies can be used to cancel out the double frequency oscillation
keeping high locking dynamics, e.g., a repetitive controller based on a DFT algorithm.
Additional improvements are added to these filters to make them frequency adaptive.
Decoupled Doubled SRF-PLL. Decoupling
e
e
o
t e
1 +
S
v
u
1 +
d
u

u
|
1 +
q
1
d
1
q
e
e
e
e
1
S
v
S
v
1
+ | et
1
1
1 1
1
1 1
1
( )
( )

cos( ) cos( )

sin( ) sin( )
Sd
S S S S
dq
dq Sq
v
t t
T V V
v
t t
o|
e u e | u
e u e | u
+
+
+ +
( ( ( +
(
= = = +
( ( (

( + ( (

v v
1
1
1 1
1
1 1
1
( )
( )

cos( ) cos( )

sin( ) sin( )
Sd
S S S S
dq
dq Sq
v
t t
T V V
v
t t
o|
e u e | u
e u e | u
( ( ( + + +
(
= = = +
( ( (

( + + + ( (

v v
' t u e ~ Near of synchronization:
1
1
1 1
1
( )
1
cos( 2 )
sin( 2 )
S S S
dq
t
V V
t t
e |
e | e u
+
( ( +
~ +
( (
+

v
1
1
1 1
1
( )
cos(2 ) cos( )
sin(2 ) sin( )
S S S
dq
t
V V
t
e |
e |
( (
~ +
( (

v
cos(( ) ) sin(( ) ) cos( )
cos( ) sin( )
sin(( ) ) cos(( ) ) sin( )
n
n
n n
Sd m m m m S
S S
n n
Sq S
v
n m t n m t V
V V
v
n m t n m t V
e e |
| |
e e |
( ( ( (
= + +
( ( ( (

(
cos(( ) ) sin(( ) ) cos( )
cos( ) sin( ) .
sin(( ) ) cos(( ) ) sin( )
m
m
m m
Sd n n n n S
S S
m m
Sq S
v
n m t n m t V
V V
v
n m t n m t V
e e |
| |
e e |
( ( ( (
= + +
( ( ( (

(
Generic decoupling cell:
cos
n
Sd
v
sin
m
Sd
v m
Sq
v
n
Sq
v
u
*
n
Sd
v
*
n
Sq
v
|
.
|
\
|
m
n
DC
n
d
n
q
u
m
d
m
q
* n
d
* n
q
n-m
This terms act as
interferences on
the SRF dq
n

rotating at ne
frequency and
viceversa
y
.

Decoupled Doubled SRF-PLL
1 +
Sd
v
1 +
Sq
v
u
1
d
1
q
|
.
|
\
|
+
1
1
DC
1 +
d
1 +
q
u
* 1 +
d
* 1 +
q
1
Sd
v
1
Sq
v
*
1 +
Sd
v
*
1 +
Sq
v
*
1
Sd
v
*
1
Sq
v
1
Sd
v
1
Sq
v
1
1
S
Sd
v
+
+
v
1 +
Sq
v
| |
o|
T
( ) o|
S
v
| |
1 +
dq
T
| |
1
dq
T
( ) abc
S
v
1 +
d
1 +
q
|
.
|
\
|
+
1
1
DC
1
d
1
q
u
* 1
d
* 1
q
}
+
i p
k k
}
e
LPF
LPF
LPF
LPF
1
*
Sq
v
+
'
*
1 +
Sq
v
2 2
q d q
v v v +
f
e
f
e
PLL input normalization
Conclusions
PLL is a very useful method that enable the grid inverters to:
Create a "clean" current reference synchronized with the grid
Comply with the grid monitoring standards
The PLL generate is able to track the frequency and phase of the input
signal in a designed settling time
By setting a higher settling time a "filtering" effect can be achieved in order
to obtain a "clean" reference even with a polluted grid.
Some PLLs need two signals in quadrature at the input.
For single-phase systems as there is only one signal available, the
orthogonal signal needs to be created artificially.
Transport Delay, Inverse Park Transformation, or Second Order
Generalized Integrators are some the methods used for quadrature signal
generation.
Adaptive notch filters canceling fundamental utility frequency are used as
phase detectors in PLLs
FLL based on a SOGI is a very effective method for single phase
synchronization
References
1. J. D. Ainsworth, The phase-locked oscillator-a new control system for controlled static
convertors, IEEE Transactions on Power Apparatus and Systems, vol. 87, no. 3, pp. 859-865,
Mar. 1968.
2. G. C. Hsieh, J. C. Hung, Phase-locked loop techniques A survey, IEEE Trans. On Ind.
Electronics, vol.43, pp.609-615, Dec.1996.
3. F. M. Gardner, Phase Lock Techniques. New York: Wiley, 1979.
4. L. D. Zhang, M. H. J. Bollen Characteristic of voltage dips (sags) in power systems, IEEE Trans.
Power Delivery, vol.15, pp.827-832, April 2000.
5. F. Blaabjerg, R. Teodorescu, M. Liserre, and A. V. Timbus, Overview of Control and Grid
Synchronization for Distributed Power Generation Systems, IEEE Trans. on Ind. Electronics, Vol.
53, Oct. 2006 Page(s):1398 1409
6. M. K. Ghartemani, M.R. Iravani, A method for synchronization of power electronic converters in
polluted and variable-frequency environments, IEEE Trans. Power Systems, vol. 19, pp. 1263-
1270, Aug. 2004.
7. M.K. Ghartemani, M.R. Iravani, A Method for Synchronization of Power Electronic Converters in
Polluted and Variable-Frequency Environments, IEEE Trans. Power Systems, vol. 19, Aug. 2004,
pp. 1263-1270.
8. H.-S. Song and K. Nam, Dual current control scheme for PWM converter under unbalanced input
voltage conditions, IEEE Trans. On Industrial Electronics, vol. 46, no. 5, pp. 953959, 1999.

References
1. P. Rodrguez, A. Luna, I. Candela, R. Teodorescu, and F. Blaabjerg, Grid Synchronization of
Power Converters using Multiple Second Order Generalized Integrators, IECON08, Nov.
2008.
2. P. Rodrguez, J. Pou, J. Bergas, J.I. Candela, R. Burgos and D. Boroyevich, Decoupled
Double Synchronous Reference Frame PLL for Power Converters Control, IEEE Trans. on
Power Electronics, March 2007.
3. P. Rodriguez, R. Teodorescu, R.; I. Candela, I.; A.V. Timbus, M. Liserre, F. Blaabjerg, New
Positive-sequence Voltage Detector for Grid Synchronization of Power Converters under
Faulty Grid Conditions, PESC '06, June 2006.
4. M Ciubotaru, Teodorescu, R., Blaabjerg, F., A New Single-Phase PLL Structure Based on
Second Order Generalized Integrator, PESC06, June 2006.
5. P. Rodrguez, A. Luna, M. Ciobotaru, R. Teodorescu, and F. Blaabjerg, Advanced Grid
Synchronization System for Power Converters under Unbalanced and Distorted Operating
Conditions, IECON06, Nov. 2006.
6. S.-K. Chung, Phase-Locked Loop for grid-connected three-phase power conversion
systems, IEE Proceedings on Electronic Power Applications, vol. 147, no. 3, pp. 213219,
2000.
7. Francisco Daniel Freijedo Fernndez, Contributions to Grid-Synchronization Techniques for
Power Electronic Converters, PhD Thesis, Vigo University, Spain, 2009

Acknowledgment
Part of the material is or was included in the present and/or past editions
of the

Industrial/Ph.D. Course in Power Electronics for Renewable Energy
Systems in theory and practice

Speakers: R. Teodorescu, P. Rodriguez, M. Liserre, J. M. Guerrero,

Place: Aalborg University, Denmark

The course is held twice (May and November) every year

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