Analog & Digital VLSI

Design
A Perspective

EE C443
Instructor-In-Charge

Digital Circuit Design
Analog verses Digital:
1940s : advent of digital computers
1960s: widespread commercial use
In past 10 to 20 years, the digital revolution
has encompassed various aspects of our life.
Analog systems that have gone digital: Still
pictures, Video recording, Audio recording,
Telephone, Traffic lines etc.
The beginning of revolution in the field of
electronics took place with analog devices and
applications like transistors and radio.
However, digital revolution took over
the world of electronic circuit design due to
following reasons favouring digital circuits
over analog one:
- reproducibility of results,
- ease of design,
- flexibility and functionality,
- programmability,
- speed,
- economy,
- and steadily advancing technology.
Analog IC Design
Renaissance due to explosive growth in wireless
telecommunication.
Examples where Analog Circuits are indispensable:
-Processing of natural signals
-Digital communications
-wireless receiver
-In retrieving data from computer hard disc
Radio Frequency (RF) IC Design in CMOS
RF CMOS IC Design resides at the
convergence of two very different engineering
traditions of conventional RF and low frequency IC
design.
CMOS Technology
Other Technologies:
BJT,MOS, BiCMOS and GaAs etc.

J E Lilienfeld: patented Idea of Metal
Oxide Silicon Field Effect Transistor
(MOSFET) in early 1930s.
Fabrication limitations: successful
realization of MOS technologies in early
1960s with NMOS for several generations.
CMOS devices: ...in mid 1960s and a
revolution in the semiconductor industry
started...
and CMOS Technology rapidly captured
the digital market because:

CMOS gates dissipated power only during
switching,
required very few devices,
dimensions of the devices could be scaled
down more easily,
and had lower fabrication cost.

CMOS technologies, after Digital Design,
was applied for Analog Design.
The possibilities of placing both analog
and digital circuits on the same chip so as to
improve the overall performance and/or
reduce the cost of packaging
made CMOS technology attractive.

MOSFETs : slower and noisier than BJTs

however, continued device-scaling led to
tremendous improvement in the speed of
MOSFETs.

Analog CMOS circuits operating at 10-100s
of GHz frequency, is now in production.

VLSI Technology
Integrated Circuits: placing multiple electronic
devices on the same substrate [Jack S Kilby]
1959-1965: Small-scale integration (SSI- up to
64 components per integrated circuit)
1965-1969: Medium-scale integration (MSI- up
to 1000 components per chip)
1969-1989: Large-scale integration (LSI- up to
one million components per chip)
1989-present: Very large-scale integration
(VLSI- more than one million components per
chip).
0.5
0.35
0.25
0.18
0.13
0.09
0.065
0.045
0.032
0.5
0.35
0.2
0.13
0.07
0.05
0.03
0.02
0.015
0.01
0.1
1
1990 1995 2000 2005 2010 2015
Years
M
i
c
r
o
n
Transistor Physical
Gate Length
Technology Nodes
Moores Law
International Technology Roadmap for Semiconductors


Moores Law + 300mm Wafer
= 4 x advantage


Moores Law:
Number of transistors per integrated
circuit would doubles every two years
- From 0.18um to 0.13um = 2x output

300mm Wafers:
- From 200mm to 300mm = 2x output
Combined output advantage:
4x output

1000
10000
100000
1000000
10000000
100000000
1970 1975 1980 1985 1990 1995 2000
Years
N
u
m
b
e
r

o
f

t
r
a
n
s
i
s
t
o
r
s
PIV
PIII
PII
Pentium
486
386
286
8008
8080
8086
and the trend of integration of transistors in
Intel microprocessors is vivid and most practical
endorsement of Moores Law
Lithography Challenges:
Deep UV lithography - 193nm to 248nm
Visible light - 400nm to 700 nm
Extreme UV lithography - 13nm
Extreme UV lithography was used last
year i.e., in 2005 for critical lithographical
steps to produce 70nm patterns.
Interconnections:
Devices are getting scaled but wires
are not scaling well.

0.18um Al interconnection: 6 metal layers
0.13um Cu interconnection : 6 metal layers
Technology Generation (um)
1 0.8 0.5 0.35 0.25 0.18 0.13
Metal Layers
2 3 4 4 5 6 6
Technology Generation vis--vis Metal Layers
Noise Sources:
Inductive coupling Magnetic field
Capacitive coupling Electric field
Inductance of VLSI metal lines become important
at operating frequencies above 1GHz.
and effect of capacitive coupling can translate
into a noise problem or a delay problem:
Aggressor
Aggressor
Victim
Victim
Noise Problem
Delay Problem
Transmission line effect also start manifesting
at high frequencies
EDA Tools
Computer Aided Design tools improve the
designers productivity and help him/her to
improve the correctness and quality of design.

In the competitive world, the use of software
tools is mandatory to obtain high quality results
on aggressive schedules.
FORTRAN, C, C++ etc : Software programming
languages, used to describe computer programs
which are sequential in nature.
For digital design:
Hardware Description Languages (HDLs)
HDLs allows the designers to model the
concurrency of processes found in hardware
elements
ADA, ABEL, VHDL, Verilog etc. = HDLs
Verilog : Gateway Design Automation
and
VHDL : DARPA (Defense Advanced Research
Projects Agency , DoD, USA)

HDLs: only logical verification in the beginning
manual translation of design in schematic circuit and
specifying interconnection between the gates
Advent of Logic Synthesis Tools : 1980s
and HDLs came into forefront of digital design
Most interesting development in IC Technology
Guess?
ever increasing chip size?
No ..no...no
It is the ever increasing opportunities to design



ones own chip !!!
Chip designed for a particular, limited product
or application are called Application Specific
Integrated Circuits (ASICs).
Types of ASICs
Full Custom ASICs:
Semi custom ASICs:
- Cell Based Integrated Circuits (CBIC)
- Masked Gate Arrays (MGA)
Programmable ASICs:
-ROM, PROM, EPROM, EEPROM, UVEPROM
-PAL, PLA
-Field Programmable Gate Arrays (FPGAs)


All FPGAs contain a regular structure of
programmable basic logic cells surrounded by
programmable interconnect.
FPGAs are ideal for low volume production
i.e., for less than 1000 products, because of the
lowest fixed costand design turnaround time
is just few hours!!!


For Digital Circuits/ASICs:
Magma (Magma Design Automation, Inc)
LeonardoSpectrum (Mentor Graphics, Inc)
FPGA Express
TM
(Synopsis, Inc)
Active CAD
TM
/Active HDL
TM
(Aldec, Inc)

CAD Tools:
and for Analog Circuits:
Virtuoso (Cadence, Inc)
T-Spice (Tanner Research, Inc)
Design Architect-IC (Mentor Graphics, Inc)

Design Flow:
Design Specification
Behavioural Description
RTL Description (HDL)
Functional Verification and Testing
Logic Synthesis
Gate-level Netlist
Logical Verification and Testing
System Partitioning
Floor-planning
Placements
Routing / Physical Layout
Physical Verification
Implementation
Challenges Ahead and Conclusions
Gates may become faster and denser, and
may use different control voltages, but how
to assure correct and reliable operation will be
a continuing concern.
The trade-offs between noise, frequency of
operation, power dissipation, tolerance of
interference and cost constitute the principle
challenge in todays wireless industry.

Will there be any barrier to extending Moores law?