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Analog Digital VLSI Design

Lecture2

http://discovery.bits-
pilani.ac.in/discipline/eee/agupta/
advd/advd.htm
What Will We Cover?
Designing chips containing lots of transistors
How basic components work (transistors, gates, flops,
memories, adders,
Complexity management: hieararchy and CAD tools
Key issues:
Performance analysis and optimization
Testing: functional and manufacturing
Power consumption, clocking, I/O, etc

Goals of this Course
Learn to design and analyze state-of-the-art
digital VLSI chips using CMOS technology
Employ hierarchical design methods
Understand design issues at the layout, transistor,
logic and register-transfer levels
Use integrated circuit cells as building blocks
Use commercial design software in the lab
Understand the complete design flow
Wont cover architecture, solid-state physics, analog
design
Superficial treatment of transistor functioning

General Principles
Technology changes fast, so it is important to
understand the general principles which would
span technology generations
optimization, tradeoffs
work as part of a group
leverage existing work: programs ,building blocks
Concepts remain the same:
Example: relays -> tubes -> bipolar transistors ->
MOS transistors

Design Strategies

Design is a continuous tradeoff to achieve
performance specs with adequate results in all
the other parameters.
Design Parameters By Which Design Success Is
Measured:
Performance Specs - function, timing, speed,
power
Size of Die - manufacturing cost
Time to Design - engineering cost and schedule
Ease of Test Generation & Testability -
engineering cost, manufacturing
cost, schedule
Manufacturability - resiliant to circuit/process
variabilities

Design cycle time
Time period from the start of chip development until the
mask tape delivery time.

Most of this time is devoted to achieving the desired
level of chip performance. Level of circuit
performance achieved depends strongly on the
design methodology
IMPACT OF DIFFERENT VLSI DESIGN STYLES ON
DESIGN
CYCLE TIME AND ACHIEVABLE CHIP PERFORMANCE

PERFORMANCE IMPROVEMENT OF A VLSI PRODUCT
FOR EACH NEW GENERATION OF MANUFACTURING
TECHNOLOGY

VLSI design flow--Y chart (D.GJASKI)
Types of IC Designs
IC Designs can be Analog or Digital
Digital designs can be one of three groups
Full Custom ASIC
Every transistor designed and laid out by hand
Programmable ASIC (Application-Specific
Integrated Circuits)
Designs synthesized automatically from a high-level
language description
Semi-Custom ASIC
Mixture of custom and synthesized modules
VLSI Design Styles
Programmable Logic Devices
Programmable Logic Device (PLD)
Field Programmable Gate Array (FPGA)
Gate Array
Standard Cell (Semi-Custom Design)
Full-Custom Design
CMOS CHIP DESIGN OPTIONS

Field Programmable Gate
Array (FPGA)
Introduction
User / Field Programmability.
Array of logic cells connected via
routing channels.
Special I/O cells.
Logic cells are mainly lookup tables
(LUT) with associated registers.
Interconnection on SRAM basis or
antifuse elements.
Xilinx XC4000 Architecture
CLB
CLB
CLB
CLB
Switch
Matrix
Programmable
Interconnect
I/O Blocks (IOBs)
Configurable
Logic Blocks (CLBs)
D Q
Slew
Rate
Control
Passive
Pull-Up,
Pull-Down
Delay
Vcc
Output
Buffer
Input
Buffer
Q D
Pad
D Q
SD
RD
EC
S/R
Control
D Q
SD
RD
EC
S/R
Control
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
H
Func.
Gen.
G
Func.
Gen.
F
Func.
Gen.
G4
G3
G2
G1
F4
F3
F2
F1
C4 C1 C2 C3
K
Y
X
H1 DIN S/R EC
XC4000E Configurable Logic
Blocks
D Q
SD
RD
EC
S/R
Control
D Q
SD
RD
EC
S/R
Control
1
1
F'
G'
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
H'
H
Func
.
Gen.
G
Func.
Gen.
F
Func.
Gen.
G4
G3
G2
G1
F4
F3
F2
F1
C4 C1 C2 C3
K
YQ
Y
XQ
X
H1 DIN S/R EC
2 Four-input function
generators (Look Up
Tables)
- 16x1 RAM or
Logic function

2 Registers
- Each can be
configured as Flip
Flop or Latch
- Independent
clock polarity
- Synchronous and
asynchronous
Set/Reset

Look Up Tables
Capacity is limited by number of
inputs, not complexity
Choose to use each function
generator as 4 input logic (LUT) or
as high speed sync.dual port
RAM
Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB
Example:
A B C D Z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

Look Up Table
Combinatorial Logic
A
B
C
D
Z
4-bit address
G
Func.
Gen.
G4
G3
G2
G1
WE
XC4000X I/O Block Diagram
Shaded areas are not included in XC4000E family.
Xilinx FPGA Routing
1) Fast Direct Interconnect - CLB to CLB
2) General Purpose Interconnect - Uses switch matrix
CLB
CLB
CLB
CLB
Switch
Matrix
Switch
Matrix
Design Flow
XC4000 XC4000 XC4000
3
Design Entry in schematic, ABEL, VHDL,
and/or Verilog. Vendors include Synopsys,
Aldec (Xilinx Foundation), Mentor,
Cadence, Viewlogic, and 35 others.
Implementation includes Placement &
Routing and bitstream generation using
Xilinxs M1 Technology. Also, analyze timing,
view layout, and more.
Download directly to the Xilinx
hardware device(s) with
unlimited reconfigurations* !!
1
2
*XC9500 has 10,000 write/erase cycles
M1 Technology
Gate Array
Introduction
In view of the fast prototyping capability, the
gate array (GA) comes after the FPGA.
Design implementation of
FPGA chip is done with user programming,
Gate array is done with metal mask design and processing.
Gate array implementation requires a two-step
manufacturing process:
1. The first phase, which is based on generic (standard)
masks, results in an array of uncommitted transistors
on each GA chip.
2. These uncommitted chips can be customized later,
which is completed by defining the metal
interconnects between the transistors of the array

Channeled vs. Channel-less
(SoG) Approaches
Small Section of a Semi-custom
Base Array Without Interconnect
Section of Semi-custom Array
with Single Level Metal
Interconnect
The GA chip utilization factor is higher
than that of FPGA.
The used chip area divided by the total chip
area.
Chip speed is also higher.
More customized design can be achieved with
metal mask designs.
Current gate array chips can implement as
many as hundreds of thousands of logic
gates.

Standard Cell Based Design
CBIC
Introduction
One of the most prevalent custom design
styles.
Also called semi-custom design style.
Requires development of a full custom mask
set.
Basic idea:
All of the commonly used logic cells are
developed, characterized, and stored in a
standard cell library.
A typical library may contain a few hundred
cells including inverters, NAND gates, NOR
gates, complex AOI, OAI gates, D-latches,
and flip-flops.
Characteristic of the Cells
Each cell is designed with a fixed height.
To enable automated placement of the cells, and
Routing of inter-cell connections.
A number of cells can be abutted side-by-side to form
rows.
The power and ground rails typically run parallel
to the upper and lower boundaries of the cell.
Neighboring cells share a common power and ground
bus.
nMOS transistors are located closer to the ground rail
while the pMOS transistors are placed closer to the
power rail.
The input and output pins are located on the
upper and lower boundaries of the cell.

Standard Cells
Standard Cell Layout
Floorplan for Standard Cell
Design
Inside the I/O frame which is reserved for I/O
cells, the chip area contains rows or columns of
standard cells.
Between cell rows are channels for dedicated inter-
cell routing.
Over-the-cell routing is also possible.
The physical design and layout of logic cells
ensure that
When placed into rows, their heights match.
Neighboring cells can be abutted side-by-side, which
provides natural connections for power and ground
lines in each row.

Full Custom Design
Introduction
The standard-cells based design is often
called semi custom design.
The cells are pre-designed for general use
and the same cells are utilized in many
different chip designs.
In the full custom design, the entire mask
design is done anew without use of any
library.
The development cost of such a design style
is prohibitively high.
The concept of design reuse is becoming
popular in order to reduce design cycle time
and cost.
Contd.
The most rigorous full custom design can
be the design of a memory cell.
Static or dynamic.
Since the same layout design is replicated,
there would not be any alternative to high
density memory chip design.
For logic chip design, a good compromise
can be achieved by using a combination of
different design styles on the same chip.
Standard cells, data-path cells and PLAs.

In real full-custom layout in which the
geometry, orientation and placement of every
transistor is done individually by the designer,
Design productivity is usually very low.
Typically 10 to 20 transistors per day,
per designer.
In digital CMOS VLSI, full-custom design is
rarely used due to the high labor cost.
Exceptions to this include the design of
high-volume products such as memory
chips, high-performance microprocessors
and FPGA masters.
Next slide shows the full layout of the Intel
486 P chip.
Good example of a hybrid full-custom
design.


Small Section of a Typical Full
Custom Layout
IMPACT OF DIFFERENT VLSI DESIGN STYLES
ON DESIGN CYCLE TIME AND ACHIEVABLE
CHIP PERFORMANCE
Comparison Among Various
Design Styles
Design Style
FPGA Gate
array
Standar
d cell
Full
custom
Cell size Fixed Fixed Fixed
height
Variable
Cell type Program
mable
Fixed Variable Variable
Cell
placement
Fixed Fixed In row Variable
Interconnectio
ns
Program
mable
Variable Variable Variable
Design time Very fast Fast Medium Slow
Structured Design Strategies

Strategies common for complex harware
and software projects.
-> Hierarchy: Subdivide the design into
many levels of sub-modules
-> Modularity: Define sub-modules
unambiguously & well defined interfaces
-> Regularity: Subdivide to max number
of similar sub-modules at each level
-> Locality: Max local connections,
keeping critical paths within module
boundaries

REGULARITY

DESIGN THE CHIP HIERARCHY INTO IDENTICAL OR
SIMILAR MODULES
EXTENDED USE OF REGULARITY SIMPLIFIES THE
DESIGN PROCESS
REGULARITY CAN EXIST AT ALL LEVELS OF
DESIGN HIERARCHY

-> Circuit Level: uniform transistor sizes rather than
manually optimizing each
device.
-> Logic Level: identical gate structures rather than
customize every gate.
-> Architecure Level: construct architecures that use a
number of identical
processor structures
MODULARITY

ADDS TO HIERARCHY AND REGULARITY
THE QUALITIES OF
WELL DEFINED FUNCTIONS AND
INTERFACES

-> Unambiguous functions
-> Well defined behavioral, structural, and
physical interfaces
-> Enables modules to be individually designed
and evaluated.

LOCALITY
TIME LOCALITY: modules see a common clock and
synchronous timing is applied.

-> Robust clock generation and distribution is critical
-> Critical paths, where possible, are to be kept within
module boundaries
-> Any global module to module signal should have an
entire clock cycle to
traverse the chip.
-> Replicate logic, if necessary, to alleviate cross-chip
crossings.
-> Locate modules in layout to minimize large or "global"
routes between
modules.

DESIGN QUALITY

-> ACHIEVE SPECIFICATIONS (Static &
Dynamic)
->DIE SIZE
->POWER DISSIPATION
-> TESTABILITY
-> YIELD AND MANUFACTURABILITY
-> RELIABILITY
->TECHNOLOGY UPDATABLE

-> TESTABILITY
+ generation of good test vectors
+ availablity of reliable test fixture at speed
+ design of testable chip
-> YIELD AND MANUFACTURABILITY
+ functional yield
+ parametric yield
->RELIABILITY
+ premature aging (Infant mortality)
+ ESD/EOS
+ latchup
+ on-chip noise and crosstalk
+ power and ground bouncing
->TECHNOLOGY UPDATABLE
+ Easily updated to new design rules

DESIGN FOR
MANUFACTURABILITY

Design goal: All fabricated circuits
meet all performance specs under all
operating conditions.
Impedements:
1. Random variations in fabrication
process.
2. Random variations in operating
conditions, e.g. VDD, Tambient.

Reality: Excessive deviations of performance
cause yield loss and increase the
unit cost of the chip.

DFM Practice:
1. Consider the effects of these expected
random in processing and operating
conditions early in the design process.
2. Circuit made as insensitive to these
variations as is practical.
3. Design to performance specs with
sufficient margins that a large fraction of
the manufactured chips pass the chip
acceptance criteria.

DFM Issues:
1. Parametric yield estimation.
2. Parametric yield maximization.
3. Worst-case analysis.
4. Variability Minimization.

PACKAGING TECHNOLGY

-> include important package related
parasitics in the chip design and
simulation
-> Package Power & Ground Planes
-> on-chip power and ground busses
-> Bond Wire Lengths -> on-chip inductive
effects
-> Thermal Resistance -> temp rise due to
on-chip power dissipation
-> Package Cost

IMPORTANT PACAKGE DESIGN
CONCERNS:

-> hermetic seals to prevent penetration of
moisture
-> thermal conductivity
-> thermal expansion coefficient
-> pin density
-> parasitic inductance and capacitance
-> alpha-paricle protection (memories)

PACKAGE TYPES
Why consider custom
integration?
There are a number of reasons why
developing a custom Integrated Circuit is
an appropriate and often essential
ingredient to the development of a
successful product:
Size. The continued market demand to
reduce the size of electronic devices, in
particular portable and hand-held devices,
requires ever higher levels of integration.
Replacing functions requiring the use of a
number of discrete components with one
IC helps achieve this goal.
Performance. By utilizing the superior
matching and tracking characteristics of
integrated circuit components, manual
adjustment of circuit parameters can often
be eliminated, while maintaining tighter
spread on key system performance specs
over the full range of operating conditions.
Additionally, critical or high-precision
specs can be trimmed at wafer test.
Cost. Replacing a number of discrete
components with a pre-tested IC
significantly reduces the test time and the
number of rejects. For large production
quantities the initial development cost will
be amortized in a short period of time,
resulting in a lower cost per unit.
Reliability. An IC is significantly more
reliable than a PCB populated with the
devices necessary to provide the
equivalent functionality using discrete
components or multiple IC's.
Copy protection. This can be the most
important incentive to consider custom
integration. Simple hardware copying is
prevented because of the exclusivity of the
custom IC.

What are some of the main
differences between system-
level and IC design?
What are the technology
options?
The three principal technologies which are
readily accessible for custom integration
are Biploar, CMOS and BiCMOS
choice between using a prefabricated
semi-custom array or undertaking a full
custom development
Managing design complexity
Hierarchydivide and conquer
Regularityrepetition of blocks
Modularity---each block complete in itself
external details
Locality---connections are mostly between
neighboring modules (internal details)
CMOS PROCESSING
N-WELL
P-WELL
TWIN-TUB
WAFER PREPARATION
defect free single crystalline lightly doped
WAFER.
Metallurgical grade silicon-electronic grade
silicon(99.99% pure)
Single crystalline structure obtained by
melting and then cooling ---czochralski
method
Ingot cut into wafers using diamond saw
Wafers are than polished to mirror finish
Process involved
Photolithography
Deposition
Oxidation
Etching
Diffusion/ion implantation

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