LECTURE

MOS CAPACITANCES
EEE C443 Analog and Digital VLSI Design

MOS CAPACITANCES
SCALING TECHNIQUES
SHORT CHANNEL EECTS

D!na"i# $e%a&io' o( MOS T'ansisto'
D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB


T%e Gate Ca)a#itan#e

*
Voltage dependent capacitances-++
d!na"i# gate #a)a#itan#e, -.n#tion
#a)a#itan#es/
*
Voltage independent capacitances/0
o&e'la) #a)a#itan#es C
GDOV
C
GSOV



MOSET CAPACITANCES




A&e'age Gate Ca)a#itan#e
Most i")o'tant 'egions in digital design1 sat.'ation and #.t+o((
Different distributions of gate capacitance for varying
operating conditions

2UNCTION Ca)a#itan#es +3 Cd4,
Cs4

2.n#tion Ca)a#itan#e






Linea'i5ing t%e 2.n#tion Ca)a#itan#e
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest

EQUIVALENT LARGE SIGNAL
AREA CAPACTIANCE


2.n#tion Ca)a#itan#e



S#aling te#%ni6.es

ROADMAP OR ULSI TECHNOLOG7
*Taken as 70% of the technology parameter
++ !"#$%!"#
Technology &eneration '(0 nm )*0 nm )(0 nm )+0 nm )00 nm 70 nm (0 nm
,ear -%roduction. )//7 )/// '00) '00+ '000 '00/ '0)'
D12!$#12! '(0$03! )&$'(0! )&$'(0! 3&$)& )0&$3& 03&$)0& '(0$03&
D12! chip -cm
'
. '4* 340 343( (40 74/ ))4' )(4*
D12! cost -55bit.)'0 00 +0 )( (4+ )4/ 0400
6afer Diameter -mm. '00 +00 +00 +00 +00 3(0 3(0
7ogic gates$cm
'
+47-*! 04'-)3! )0-)0! )*-'3! +/-30! *3-03! )*0-)00!
7ogic chip -cm
'
. +-34* +43-* +4*(-*4( 34+-/ (4'-)0 04'-)) 74(-)+
8re9uency -&:. 04+-047( 04(-)4' 040-)43 047-)40 04/-'40 )4'-'4( )4(-+40
cost -m 5T. +000 )7+( )000 (*0 '(( ))0 3/
2#;< 1= cost -m 5T. (0 '( '0 )( )0 ( '4(
%o>er$chip -6. 70 /0 ))0 )+0 )00 )70 )7(
%o>er #upply '4(-)4*V )4*-)4(V )4(-)4'V )4(-)4' V )4'-04/V 04/-040V 040-04(
7evels of !etal 0 0-7 7 7 7-* *-/ /
"?ide Thickness -nm. 3-( +-3 '-+ '-+ )4(-' @)4( @)
AB at <hannel -nm. (0-)00 +0-7' +0-00 '0-(' '0-30 )(-+0 )0-'0
AB <ontact -nm. )00-'00 70-)30 00-)'0 (0-)00 30-*0 )(-+0 )0-'0
ominal 7eff -m.* )30-')0 )00-)() *3-)'0 7+-)0/ (0-*3 33-(3 '*-3'
7eff Variation @'0% @'0% @'0% @'0% @'0% @'0% @'0%
;d sat - $ m . ++ 000$'*0 000$'*0 000$'*0 000$'*0 000$'*0 000$'*0 000$'*0
;off -n2$ m . ) ) + + + )0 )0
umber of ;$" pins )3(0 '000 '300 +000 3000 (300 7+00'
1=#C7T#D
Density$<hip D
Delay$<kt t
%o>er$<ircuit %
#<27;& T:="1,

EEE C443 Analog and Digital VLSI Design
8%! S#aling9
*
Te#%nolog! s%'in:s 4! ;</=>gene'ation
*
8it% e&e'! gene'ation #an integ'ate ?@ "o'e
(.n#tions )e' #%i)A #%i) #ost does not in#'ease
signi(i#antl!
*
Cost o( a (.n#tion de#'eases 4! ?@
*
$.t B
0
HoC to design #%i)s Cit% "o'e and "o'e (.n#tions9
0
Design enginee'ing )o).lation does not do.4le e&e'!
tCo !ea'sB
*
Hen#e, a need (o' "o'e e((i#ient design "et%ods
0
E@)loit di((e'ent le&els o( a4st'a#tion

Te#%nolog! s#aling
*
C.''entl!, te#%nolog! s#aling %as a t%'ee(old o4-e#ti&e1
0 Red.#e t%e gate dela! 4! 3<D E43D in#'ease in ('e6.en#!F
0 Do.4le t%e t'ansisto' densit!
0
Sa&ing G<D o( )oCe' Eat 43D in#'ease in ('e6.en#!F
*
HoC is s#aling a#%ie&ed9
0
All t%e de&i#e di"ensions Elate'al and &e'ti#alF a'e 'ed.#ed
4! H>
0 Con#ent'ation densities a'e in#'eased 4!
0
De&i#e &oltages 'ed.#ed 4! H> Enot in all s#aling "et%odsF
0 T!)i#all! H> I </= E3<D 'ed.#tion in t%e di"ensionsF

EEE C443 Analog and Digital VLSI Design
S#aling Models

ULL SCALING+++in a##o'dan#e Cit% )oison e6.ation
E
si
-d
'
V-x. $dx
'
. F G H-x. F 9 I -N
D
+
- N
2
-
- n + p.
*
T%e scaling variables a'e1
0 S.))l! &oltage1 V
dd
V
dd
> s
0
Gate lengt%1 L L > s
0
Gate Cidt%1 8 8 > s
0 Gate+o@ide t%i#:ness1 t
o@
t
o@
> s
0 2.n#tion de)t%1 J
-
J
-
> s
0 S.4st'ate do)ing1 N
A
N
A
s
T%is is #alled constant field s#aling 4e#a.se t%e ele#t'i#
(ield a#'oss t%e gate+o@ide does not #%ange C%en t%e
te#%nolog! is s#aled

#ome conse9uences of full scaling
E
si
-d
'
V-x. $dx
'
. F G H-x. F 9 I N
D
3<D s#aling in t%e #onstant (ield 'egi"e Es I H/43, H>s I </=F1
Device$die areaD
8 L EH>sF
?
I </4K
0
In )'a#ti#e, "i#'o)'o#esso' die si5e g'oCs a4o.t ?GD )e'
te#%nolog! gene'ationL T%is is a 'es.lt o( added
(.n#tionalit!/
*
Transistor density1
E.nit a'eaF >E8 LF s
?
I ?/<4
0 In )'a#ti#e, "e"o'! densit! %as 4een s#aling as
e@)e#ted/
Enot t'.e (o' "i#'o)'o#esso'sBF

#ome conse9uences of full scaling
*
&ate capacitance1
8 L > t
o@
H>s I </=
* Drain current1
E8>LF EV
?
>t
o@
F H>s I </=
*
&ate delay1
EC VF > I H>s I </=
'e6.en#! s I H/43
0 In )'a#ti#e, "i#'o)'o#esso' ('e6.en#! %as do.4led e&e'! te#%nolog!
gene'ation E? to 3 !ea'sFL T%is (aste' in#'ease 'ate is d.e to tCo (a#to's1
* t%e n."4e' o( gate dela!s in a #lo#: #!#le de#'eases Cit% ti"e Et%e designs
4e#o"e %ig%l! )i)elinedF
* ad&an#ed #i'#.it te#%ni6.es 'ed.#e t%e average gate delay beyond +0% )e'
gene'ation/

#ome conse9uences of full scaling
*
%o>er dissipation1
C V
?
( EH>sF
?
I </4K
*
%o>er density1
EH>t
o@
V
?
( F > a'ea H
*
A#ti&e #a)a#itan#e>.nit+a'ea1PoCe' dissi)ation is a (.n#tion o(
t%e o)e'ation ('e6.en#!, t%e )oCe' s.))l! &oltage and o( t%e
#i'#.it si5e En."4e' o( de&i#esF/
I( Ce no'"ali5e t%e )oCe' densit! to V
?
( Ce o4tain t%e a#ti&e
#a)a#itan#e )e' .nit a'ea (o' a gi&en #i'#.it/ T%is )a'a"ete' #an
4e #o")a'ed Cit% t%e o@ide #a)a#itan#e )e' .nit a'ea1
H>t
o@
s I H/43
0
In )'a#ti#e, (o' "i#'o)'o#esso's, t%e a#ti&e #a)a#itan#e>.nit+
a'ea onl! in#'eases 4etCeen 3<D and 3GD/ T%.s, t%e tCo
(old i")'o&e"ent in logi# densit! 4etCeen te#%nologies is
not a#%ie&ed/

I( t%e )oCe' s.))l! &oltage is "aintained
#onstant t%e s#aling is #alled constant
voltage/
In t%is #ase, t%e ele#t'i# (ield a#'oss t%e gate+
o@ide in#'eases as t%e te#%nolog! is s#aled
doCn/
Due to gate-o?ide breakdo>nJ belo>
04*Km only Lconstant fieldM scaling is
used4
<onstant voltage scaling

*
T%e scaling variables a'e1
0 S.))l! &oltage1 V
dd
V
dd
0
Gate lengt%1 L L > s
0
Gate Cidt%1 8 8 > s
0 Gate+o@ide t%i#:ness1 t
o@
t
o@
> s
0 2.n#tion de)t%1 J
-
J
-
> s
0 S.4st'ate do)ing1 N
A
N
A
s
?

#ome conse9uences of <V scaling
E
si
-d
'
V-x. dx
'
. F G H-x. F 9 I N
D
De&i#e>die a'ea1
8 L EH>sF
?
I </4K
T'ansisto' densit!1
E.nit a'eaF >E8 LF s
?
I ?/<4

#ome conse9uences of <V scaling
*
Gate #a)a#itan#e1
C
GS
8 L > t
o@
H>s I </=
*
D'ain #.''ent1
E8>LF EV
?
>t
o@
F s I H/43
*
Gate dela!1
EC
GS
V
DS
F > I
D
H> s
?
I </4K
*
'e6.en#! s
?
I ?/<4

#ome conse9uences of <V scaling
*
%o>er dissipation1
VdsMIds I C
GS
V
?
( s I H/43
*
%o>er densityD
EP>AREAF H>t
o@
V
?
( s
3
I ?/K?
*
2ctive capacitance$unit-area1
)oCe' densit!> EV
?
( F s
EEE C443 Analog and Digital VLSI Design

%arameter <onstant 8ield <onstant Voltage
S.))l! &oltage EV
dd
F H> H
Lengt% ELF H> H>
8idt% E8F H> H>
Gate+o@ide t%i#:ness Et
o@
F H> H>
2.n#tion de)t% EJ
-
F H> H>
S.4st'ate do)ing EN
A
F
Ele#t'i# (ield a#'oss gate o@ide EEF H
De)letion la!e' t%i#:ness H> H>
Gate a'ea EDie a'eaF H>
?
H>
?
Gate #a)a#itan#e EloadF ECF H> H>
D'ain+#.''ent EI
dss
F H>
T'ans#ond.#tan#e Eg
"
F H
Gate dela! H> H>
?
C.''ent densit!
3
DC N D!na"i# )oCe' dissi)ation H>
?

PoCe' densit! H
3
PoCe'+Dela! )'od.#t H>
3
H>
#caling
Variables
Device
1epercussion
<ircuit
1epercussion
s.""a'!

#<27;& "8 <"DC<T"1#
<2%2<;T2<= < <$a
1=#;#T2<= 1 a1
T;!= <"#T2T 1< 1<
<C11=T D=#;T, N aN

*
RIOL>Ct
* CIP
o@
A>t
EEE C443 Analog and Digital VLSI Design

*
;nterconnects scalingD
0
Hig%e' densities a'e onl! )ossi4le i( t%e inte'#onne#ts
also s#ale/
0
Red.#ed Cidt% in#'eased 'esistan#e
0
Dense' inte'#onne#ts %ig%e' #a)a#itan#e
0
To a##o.nt (o' in#'eased )a'asiti#s and integ'ation
#o")le@it! more interconnection layers a'e added1
* t%inne' and tig%te' la!e's lo#al inte'#onne#tions
* t%i#:e' and s)a'se' la!e's glo4al inte'#onne#tions and
)oCe'
Inte'#onne#ts a'e s#aling as e@)e#ted
EEE C443 Analog and Digital VLSI Design

EEE C443 Analog and Digital VLSI Design
S#aling Models 0 Long C%annel

SHORT CHANNEL EECTS

T%e S.4+Mi#'on MOS T'ansisto'
O Threshold Variations
O %arasitic 1esistances
O Velocity #auturation and !obility Degradation
O #ubthreshold <onduction
O 7atchup

T%'es%old Va'iations
V
T
L
Long+#%annel t%'es%old
LoC V
DS
t%'es%old
T%'es%old as a (.n#tion o(
t%e lengt% E(o' loC V
DS
F
D'ain+ind.#ed 4a''ie' loCe'ing
E(o' loC LF

Pa'asiti# Resistan#es
W
L
D
Drain
Drain
contact
Polysilicon gate
D S
G
R
S
R
D
V
GS,eff

Velo#it! Sat.'ation EHF
E
(
V/

m)
E
sat
= 1.5

n

(
c
m
/
s
e
c
)

sat
= 10
7
Constant mobility (slope = )
constant velocity
E
t
(
V/

m)

n

(
c
m
2
/
V
s
)

n0
(b) Mobility egraation
(a) Velocity sat!ration
0
700
2"0
100

Velo#it! Sat.'ation E?F
V
DS
(V)
I
D

(
m
A
)
L
i
n
e
a
r

D
e
p
e
n
d
e
n
c
e
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
V
GS
= 1
0.0 1.0 2.0 3.0 4.0 5.0
0.5
1.0
1.5
(a) I
D
as a function of V
DS
(b) I
D
as a function of V
GS
(for V
DS
= 5 V)
.
0.0 1.0 2.0 3.0
V
GS
(V)
0
0.5
I
D

(
m
A
)
Linear Dependence on V
GS

S.4+T%'es%old Cond.#tion
</< H/< ?/< 3/<
V
GS
EVF
H<
H?
H<
H<
H<
Q
H<
R
H<
4
H<
?
l
n
E
I
D
F

E
A
F
S.4t%'es%old e@)onential 'egion
Linea' 'egion
V
T

Lat#%.)
(a) #rigin o$ latc%!p
(b) &'!ivalent circ!it
V
DD
R
psubs
R
nwell
p-source
n-source
n
+
n
+
p
+
p
+
p
+
n
+
p(s!bstrate
R
psubs
R
nwell
V
DD
n()ell

SPICE MODELS
7evel )D 7ong <hannel =9uations - Very #imple
7evel 'D %hysical !odel - ;ncludes Velocity
#aturation and Threshold Variations
7evel +D #emi-=mperical - Pased on curve fitting
to measured devices
7evel 3 -P#;!.D =mperical - #imple and %opular

itting le&el+H "odel (o' "an.al
anal!sis
V
GS
I G V
V
DS
I G V
V
DS
I
D
Long+#%annel
a))'o@i"ation
S%o't+#%annel
I+V #.'&e
Region o(
"at#%ing
Sele#t k

and

s.#% t%at 4est "at#%ing is o4tained S V

gs
I V
ds
I V
DD

Te#%nolog! E&ol.tion

P'o#ess Va'iations
Devices parameters vary bet>een runs and even on
the same dieQ
Variations in t%e process parameters* s!c% as imp!rity concentration en(
sities* o+ie t%ic,nesses* an i$$!sion ept%s- .%ese are ca!se by non(
!ni$orm conitions !ring t%e eposition an/or t%e i$$!sion o$ t%e
imp!rities- .%is intro!ces variations in t%e s%eet resistances an transis(
tor parameters s!c% as t%e t%res%ol voltage-
Variations in t%e imensions o$ t%e evices* mainly res!lting $rom t%e
limite resol!tion o$ t%e p%otolit%ograp%ic process- .%is ca!ses (W/L)
variations in M#/ transistors an mismatc%es in t%e emitter areas o$
bipolar evices-


I")a#t o( De&i#e Va'iations
H/H< H/?< H/3< H/4< H/G< H/R<
L
eff
Ein ""F
H/G<
H/=<
H/K<
?/H<
D
e
l
a
!

E
n
s
e
#
F
0</K< 0</Q< 0</=< 0</R< 0</G<
V
Tp
EVF
H/G<
H/=<
H/K<
?/H<
D
e
l
a
!

E
n
s
e
#
F
Delay of 2dder circuit as a function of variations in L and V
T

Lat#%.)
(a) #rigin o$ latc%!p
(b) &'!ivalent circ!it
V
DD
R
psubs
R
nwell
p-source
n-source
n
+
n
+
p
+
p
+
p
+
n
+
p(s!bstrate
R
psubs
R
nwell
V
DD
n()ell