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SOURCES OF POWER DISSIPATION

By
Y Anil Kumar,
1333D5701,
M.TECH(VLSI),1
ST
YEAR, 2
ND
SEM
Topics to be covered
Introduction to need for low power circuit
Switching Power Dissipation
Short Circuit Power Dissipation
Leakage power dissipation
Reverse bias pn leakage current
Sub threshold leakage
INTRODUCTION TO NEED FOR LOW POWER
CIRCUITS
Power dissipation is the main constrain when it
comes to Portability
Scaling of technology node increases power-
density more than expected
CMOS technology beyond 65nm node
represents a real challenge for any sort of
voltage and frequency scaling Starting from
120nm node.
Between 90nm to 65nm the dynamic power
dissipation is almost same whereas there is
~5% higher leakage/mm2.

CONTD
An alternative to solve this problem could mean
accepting either the large cost and volume of the
cooling subsystem or curtailing micro processor
functionality
Sources of power dissipation
Due to Short circuit currents
Due to signal transitions(switching dissipation)
Due to leakage currents
When supply voltage is being scaled down to reduce
dynamic power, lower threshold voltages are
maintained.
Lower Vth, greater the stand by leakage current.

SHORT CIRCUIT DISSIPATION
While Vth< Vin<Vdd-|Vtp|
both the NMOS and
PMOS sub network
conduct and short circuit
path for direct current flow
from Vdd to ground
terminal.
The short circuit
dissipation decreases both
in absolute terms and as a
fraction of total power
dissipation as the output
load is increased

SHORT CIRCUIT POWER DISSIPATION
However if the inverter is lightly loaded,
causing output rise and fall times to be
shorter than the input rise and fall times,
the short circuit dissipation increases to
become comparable to dynamic
dissipation.
Therefore minimize dissipation, an inverter
should be designed in such a way that rise
and fall times are about equal to the output
rise and fall times.
SWITCHING DISSIPATION
For an inverter the average
dynamic dissipation can be
obtained by summing the
average dynamic
dissipation in the NMOS
and PMOS.
Dynamic power is
proportional to the
switching frequency and the
square of power supply
voltage.
STATIC POWER DISSIPATION
When Vth decreases sub threshold leakage
current decreases.
From year wise analysis of ITRS
Gate length oxide thickness, power supply
showed gradual decrease but the
transconductance increased

Energy per device switching transition ,dynamic
dissipation decreases and the static power
dissipation increases

Ioff is influenced by
Threshold voltage
Channel physical dimensions
Channel surface doping profile
Drain/source junction depth
Gate oxide thickness
Power supply Vdd
Ioff in long channel is dominated by leakage from
drain well and well drain substrate reverse bias
junctions
Short channel transistors have Ioff large compared to
leakage current
Six short channel leakage mechanisms are
described. They are
I1- reverse bias pn junction leakage current
I2- sub threshold leakage current
I3- gate oxide leakage current
I4- gate current due to hot carrier injection
I5- gate induced drain leakage
I6- channel punch through current
I1, I2, I5 and I6 are Off state leakage mechanisms
I3 occurs in ON and OFF conditions due to oxide
tunneling.
I4 can occur in OFF state , but more typically due to
high electric field driving active mode operation.
I1- REVERSE BIAS PN JUNCTION LEAKAGE
CURRENT
Due to
Minority carrier drift or diffusion near the edge of
depletion region
Due to electron hole pair generation in depletion
region
Zener and band to band tunneling (n and p heavily
doped)
Additional leakage can occur between the drain and
well junction from gated diode device action or
carrier generation in the drain to well depletion
regions with influences of the gate on these current
components.
I1 is a function of junction area and doping
concentration and strongly correlates with
temperature.

I2- SUB THRESHOLD LEAKAGE CURRENT
Occurs between source and
drain when Vgs<Vth
In weak inversion sub
threshold current is due to
drift current, which is
negligible
In strong inversion region sub
threshold conduction is
dominated by the diffusion
current.
Weak inversion typically
dominates modern device
OFF state leakage due to low
Vth that is used

CONTD.
As device dimensions and the supply voltage are
being scaled down to enhance performance, power
efficiency, and reliability the sub threshold
characteristic becomes a limitation on how small
power supply can be used
A low value for sub threshold slope is desirable
From the expression we can it can be noted that St
can be made smaller using a thinner oxide layer to
reduce t
ox
or by using a lower substrate doping
concentration.
Changes in operating conditions, namely lower
temperature or a substrate bias, also cause St to
decrease

QUANTUM EFFECT
In scaled devices, due to high electric field at
the surface and the high substrate doping, the
quantization of inversion layer energy modulates
Vth.
Quantum mechanical behavior of the electrons
increases Vth, there by reducing the sub
threshold current, since more band bending is
required to populate the lowest sub band, which
is at an energy higher than at the bottom of the
conduction band
When
s
is higher than 10
6
V/cm, electrons
occupy only in the lowest sub band.

Increase in E
0
increases V
QM
.
With technology scaling, due to high doping
and high oxide field, resulting in an increase
in E
0

REFERENCES
Low-Voltage, Low-Power VLSI Subsystems
Kiat-Seng Yeo, Kaushik Roy, TMH
Professional Engineering.
http://www.eeherald.com/section/design-
guide/Low-Power-VLSI-Design.html
THANK YOU