Device Servicing

Programmed I/O
CPU has direct control over I/O
Sensing status
Read/write commands
Transferring data
CPU waits for I/O module to complete
operation
Wastes CPU time
Programmed I/O - detail
CPU requests I/O operation
I/O module performs operation
I/O module sets status bits
CPU checks status bits periodically
I/O module does not inform CPU directly
I/O module does not interrupt CPU
CPU may wait or come back later
I/O Commands
CPU issues address
Identifies module (& device if >1 per module)
CPU issues command
Control - telling module what to do
e.g. spin up disk
Test - check status
e.g. power? Error?
Read/Write
Module transfers data via buffer from/to device

Interrupt Driven I/O
Overcomes CPU waiting
No repeated CPU checking of device
I/O module interrupts when ready
Interrupt Driven I/O
Basic Operation
CPU issues read command
I/O module gets data from peripheral whilst
CPU does other work
I/O module interrupts CPU
CPU requests data
I/O module transfers data

Simple Interrupt
Processing
CPU Viewpoint
Issue read command
Do other work
Check for interrupt at end of each instruction
cycle
If interrupted:-
Save context (registers)
Process interrupt
Fetch data & store
Device Drivers
What are Device Drivers
A program that controls a device
LAN Driver, Video Driver, USB Driver
Acts like a translator between the device and
programs that use the device
Converts generic commands issued by the
Application into specific commands understood by
the device.
Interacts with Hardware at the Physical level
Devices are controlled from the Applications
through their respective drivers.
Device Driver Interface
Device Driver

Operating System
Application
User Mode Kernel Mode
Type of Device Drivers
Character Mode: Serial Communication






Block Mode: Floppy Disk,Hard Disk
Linux/Unix Device Drivers
A Device driver can be compiled directly into
the kernel, or loaded at runtime as a module.
The VFS switch is the interface between the
kernel and the device.
Devices are presented to normal programs
as special files.
The device driver consists of the device level
implementation of the generic file system
calls
Writing physical Device Driving
ISRs
There are three sets of device registers
1. Data registers
2. Control registers:-It controls all actions of
the device.
A device initializes or closes by setting &
resetting the control register bits.
3. Status registers:-Status register bits
reflects flags for the status of the device.

Interrupts
Interrupts
An interrupt is an asynchronous signal from
hardware indicating the need for attention or a
synchronous event in software indicating the need
for a change in execution.
A hardware interrupt causes the processor to save
its state of execution via a context switch, and begin
execution of an interrupt handler.
Software interrupts are usually implemented as
instructions in the instruction set, which cause a
context switch to an interrupt handler similar to a
hardware interrupt.
Maskable Interrupts
The processor can inhibit certain types of interrupts by use of a
special interrupt mask bit. This mask bit is part of the
flags/condition code register, or a special interrupt register. In the
8086 microprocessor if this bit is clear, and an interrupt request
occurs on the Interrupt Request input, it is ignored.
Non-Maskable Interrupts
There are some interrupts which cannot be masked out or
ignored by the processor. These are associated with high priority
tasks which cannot be ignored (like memory parity or bus faults).
In general, most processors support the Non-Maskable Interrupt
(NMI). This interrupt has absolute priority, and when it occurs,
the processor will finish the current memory cycle, then branch to
a special routine written to handle the interrupt request.
Software instruction related
interrupt sources
Exceptions :- Software exception is a run
time exceptional condition which causes a
diversion to another routine called exception.
Trap flag
These are certain instruction like SW1 in
68H11, INT0 in 8086 processor.


Assigning of priorities to
interrupts
Assume 4 interrupts
1.watchdog timer, 2.timer input, 3.timer
output, 4.A/D converter.
Interrupt Latency
The time interval from when the interrupt is first asserted to the
time the CPU recognises it. This will depend much upon whether
interrupts are disabled, prioritized and what the processor is
currently executing. At times, a processor might ignore requests
whilst executing some indivisible instruction stream (read-write-
modify cycle). The figure that matters most is the longest
possible interrupt latency time.
Interrupt Response Time
The time interval between the CPU recognising the interrupt to
the time when the first instruction of the interrupt service routine
is executed. This is determined by the processor architecture and
clock speed.
Timer
Watchdog timer
Counter
S/W Tools in Designing of an
Embedded System
Editor
Interpreter
Compiler
Assembler
Cross Assembler
Simulator


Timers and counters
Timers measures time intervals
It can generate event at specific time
Determine duration between two intervals
Measures time by counting pulses that occur
on an input clock signal having known period

counters
General version of timer
It counts pulses on some other input signal
Combination of counters and timers use to
measures rates such as counting number of
times a car wheel rotates in one second in
order to determine cars speed
To use timer we must configure its input and
monitor its output
Watchdog timer
A special type of timer with a real time value
Instead of timer generating signal for every x
time units, we must generate a signal for the
timer every x time unit
If we failed to generate signal in time, then
timer times out


Watchdog timer used in embedded system to
restart it in case of failure
In case of program failure such as entering
an undesired infinite loop or waiting for input
event that never occurs
Ex: ATM timeout using watchdog timer
Features of 68HC12
microcontroller
16-bit CPU
Supports a standard 64KB address space
Some members support a paged memory
expansion scheme that increases the standard
memory space by means of predefined windows
in address space
768 bytes to 4KB of on-chip EEPROM
1KB to 12KB of on-chip SRAM
8-bit or 10-bit A/D converter
Features of 68HC12
microcontroller
32KB to 256KB of on-chip flash or ROM memory
Timer module that includes input capture, output
compare, and pulse accumulator functions. This
is the most complicated module in the 68HC12
microcontroller.
Pulse-width modulation (PWM)
Synchronous peripheral interface (SPI)
Asynchronous serial communication interface
(SCI)
Byte data link communication (BDLC)
Features of 68HC12
microcontroller
Controller area network (CAN)
Computer operating properly (COP)
watchdog timer
Single-wire background debug mode (BDM)
Instructions for supporting fuzzy logic
General-purpose accumulator A and B:-
Both A and B are 8-bit registers. Most arithmetic
functions are performed on these two registers.
These two accumulators can also be
concatenated to form a single 16-bit
accumulator that is referred to as the D
accumulator.
Index registers X and Y:-
These two registers are used mainly in
forming operand addresses during the
instruction execution process. However, they
are also used in several arithmetic
operations.
Stack pointer (SP):-
A stack is a first-in-first-out data structure.
The 68HC12 has a 16-bit stack pointer that
points to the top byte of the stack (shown in
Figure 1.4). The stack grows toward lower
addresses.
Program counter (PC) :-
The 16-bit PC holds the address of the next
instruction to be executed.
After the execution of an instruction, the PC
is incremented by the number of bytes of the
executed instruction.
Condition code register (CCR) :-
This 8-bit register is used to keep track of the
program execution status, control the
execution of conditional instructions, and
enable/disable the interrupt handling.
The contents of the CCR register are shown
in Figure.
The status bits reflect the results of CPU
operation as it executes instructions.
The five flags are half carry (H), negative
(N), zero (Z), overflow (V), and carry/borrow
(C).
S Control Bit:-
Setting the S bit disables the STOP instruction.
Execution of a STOP instruction causes the on-
chip oscillator to stop. This may be undesirable
in some applications.
If the CPU encounters a STOP instruction while
the S bit is set, it is treated like a no
operation(NOP) instruction, and continues to the
next instruction.
X Mask Bit:-
The XIRQ input is an updated version of the
NMI input found on earlier generations of
MCUs. Non-maskable interrupts are typically
used to deal with major system failures.
I Mask Bit
The I bit enables and disables maskable
interrupt sources. By default, the I bit is set to
one during reset. An instruction must clear
the I bit to enable maskable interrupts.
While the I bit is set, maskable interrupts can
become pending and are remembered
The 68HC12 supports the
following types of data:
Bits
5-bit signed integers
8-bit signed and unsigned integers
8-bit, 2-digit binary-coded-decimal numbers
9-bit signed integers
16-bit signed and unsigned integers
16-bit effective addresses
32-bit signed and unsigned
Memory Organization

The standard CPU12 address space is 64
Kbytes. Some M68HC12 devices support a
paged memory expansion scheme that
increases the standard space by means of
predefined windows in address space
Instruction Queue
The CPU12 uses an instruction queue to
buffer program information. The mechanism
is called a queue rather than a pipeline
because a typical pipelined CPU executes
more than one instruction at the same time.



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