Fabrication Process

Wafer preparation
Metallurgical grade silicon-electronic grade silicon(99.99% pure)
Single crystalline structure obtained by melting and then cooling ---
Czochralski method
Ingot cut into wafers using diamond saw
Wafers are than polished to mirror finish

Silicon Wafer creation
CMOS Inverter

0: Introduction 8
Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
0: Introduction 9
Well and Substrate Taps
Substrate must be tied to GND and n-well to V
DD
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
substrate tap
well
tap
n+ p+
0: Introduction 10
Inverter Top View

GND V
DD
Y
A
substrate tap
well tap
nMOS transistor pMOS transistor
0: Introduction 11
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
Fabrication Process

Blank Wafer
Oxidation
Photolithography
N-well formation
Polysilicon gate formation
n+ diffusion
pp+ diffusion
metalization
0: Introduction 13
Fabrication Steps
Start with blank wafer (typically p-type where NMOS is created)
p substrate
Oxidation
Grow Sio
2
on top of Si wafer
Wet oxidation (900-1000c), 2:1 mixture of H
2
and

O
2

(pyrogenic oxidation)
Dry oxidation-(1200c) O
2


p substrate
SiO
2
Photoresist
Photo resist
Photoresist is a light-sensitive organic polymer
Property changes when exposed to light

Two types of photo resists (positive or negative)
Positive resists can be removed if exposed to UV light
Negative resists cannot be removed if exposed to UV light




p substrate
SiO
2
Photoresist
Lithography
Expose photoresist to Ultra-violate (UV) light through the n-well
mask
Strip off exposed photo resist with chemicals
p substrate
SiO
2
Photoresist
n-well mask
Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed
N-well pattern is transferred from the mask to Sio
2
surface; creates
an opening to the silicon surface

p substrate
SiO
2
Photoresist
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
p substrate
SiO
2
N-well
N-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic-rich gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2 shields (or masks) areas which remain p-type

n well
SiO
2
Strip Oxide
Strip off the remaining oxide using HF
Subsequent steps involve similar series of steps
p substrate
n well
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

Thin gate oxide
Polysilicon
p substrate
n well
0: Introduction 22
Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
Self-Aligned Process
Use gate-oxide/poly silicon and masking to expose where n+
dopants should be diffused or implanted

p substrate
n well
0: Introduction 24
N-diffusion/implantation
Pattern oxide and form n+ regions
N-diffusion forms nMOS source, drain, and n-well contact
Polysilicon is better than metal for self-aligned gates because it doesnt
melt during later processing
p substrate
n well
n+ Diffusion
0: Introduction 25
N-diffusion cont.
Historically dopants were diffused
Usually high energy ion-implantation used today
But n+ regions are still called diffusion

n well
p substrate
n+ n+ n+
0: Introduction 26
N-diffusion cont.
Strip off oxide to complete patterning step
Source and drain are separated by channel under the gate self
aligned process
n well
p substrate
n+ n+ n+
0: Introduction 27
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain
and substrate contact
p+ Diffusion
p substrate
n well
n+ n+ n+ p+ p+ p+
0: Introduction 28
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide (FO)
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Contact
Contacts
0: Introduction 30
Metalization
Sputter on aluminum over whole wafer
Gold is used in newer technology
Pattern to remove excess metal, leaving wires

p substrate
Metal
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Metal
Metalization cross section
Over glass and pad openings(Passivation)

A protective glass layer is added over the surface
The protective layer consists of:
A layer of SiO
2

Followed by a layer of silicon nitride
The SiN layer acts as a diffusion barrier against contaminants
(passivation)
OpeningConnection to I/O pads, test probes
Bumping

p substrate
p substrate
SiO
2
p substrate
SiO
2
Photoresist
p substrate
SiO
2
Photoresist
N-well Fabrication overview
p substrate
SiO
2
Photoresist
p substrate
SiO
2
n well
SiO
2
p substrate
n well
Thin gate oxide
Polysilicon
p substrate
n well
p substrate
Thin gate oxide
Polysilicon
n well
p substrate
n well
p substrate
n well
n well
p substrate
n+ n+ n+
n well
p substrate
n+ n+ n+
p substrate
n well
n+ n+ n+ p+ p+ p+
p substrate
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
p substrate
Metal
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
CMOS fabrication process
overview 8-37
Twin-Tub (Twin-Well) CMOS Process


Fabrication Process

Crystal growth
Wafers
Pattering:-Repeated steps of Lithography Diffusion and
Etching
Testing
Packaging
Dicer:- Cut the Patterned wafers into dice
Lithography
The lithographic sequence is repeated for each physical layer used to
construct the IC. The sequence is always the same:
Photo-resist application
Printing (exposure)
Development
Etching

Photomaskreticle
Steppermoves reticle
Types of printing:
Projection printing
Contact printing
Proximity printing
Light source
Mercury lamp 436nm or 365 nm
Lasers-248nm (deep UV)
Argon fluoride laser-193nm

Silicon oxidation

Wet oxidation (900-1000c), 2:1 mixture of H
2
and

O
2
(pyrogenic
oxidation)
Dry oxidation-(1200c) O
2

Atomic Layer deposition- process in which a thin chemical layer
(material A) is attached to a surface and then a chemical (material B) is
introduced to produce a thin layer of the required layer (i.e., Si02).
The process is then repeated and the required layer is built up layer by
layer.
Contacts and Metalization
Contact- cut mask
Metal mask
Metal 2

Another layer of LTO CVD oxide is added
Via openings are created
Metal 2 is deposited and patterned

n-well
p-type
n+
p+
Via
metal 1
metal 2
Circuit Under Design
V
DD
V
DD
V
in
V
out
M1
M2
M3
M4
V
out2
Circuit Layout
gnd
vdd
Start Material
Starting wafer: n-type with
doping level = 10
13
/cm
3
* Cross-sections will be
shown along vertical line A-A
A
A
N-well Construction
(1) Oxidize wafer
(2) Deposit silicon nitride
(3) Deposit photoresist
N-well Construction
(4) Expose resist using n-well
mask
N-well Construction
(5) Develop resist
(6) Etch nitride and
(7) Grow thick oxide
N-well Construction
(8) Implant n-dopants (phosphorus)
(up to 1.5 m m deep)
P-well Construction
Repeat previous steps
Grow Gate Oxide
0.055 mm thin
Grow Thick Field Oxide
Uses Active Area mask
Is followed by
threshold-adjusting implants
0.9 mm thick
Polysilicon layer
Source-Drain Implants
n+ source-drain implant
(using n+ select mask)
Source-Drain Implants
p+ source-drain implant
(using p+ select mask)
Contact-Hole Definition
(1) Deposit inter-level
dielectric (SiO
2
) 0.75 mm
(2) Define contact opening
using contact mask
Aluminum-1 Layer
Aluminum evaporated
(0.8 mm thick)
followed by other metal
layers and glass
Advanced Metalization