ARM Processor

Chapter 1: ARM Embedded Systems

Lecture 1
10/11/2014 Swamy, IT
ARM based products
Swamy, IT 10/11/2014
Washing
Machine
Coffee Machine
ARM based products
Swamy, IT 10/11/2014
iPOD
ARM based products
Swamy, IT 10/11/2014
Wireless LAN industrial
printer
Set Top Box
ARM based products
Swamy, IT 10/11/2014
Features driven the ARM processor
design
Portable embedded systems requires some
form of battery power
High code density: Limited memory devices
ES are price sensitive
Area of the die taken by the embedded
processor.
Time to market( development time & testing
time)


Swamy, IT 10/11/2014
Why is 32-bit outgrowing the MCU
market?
Customers ask for more
performance
Advanced communication
Advanced human interfaces

8-bit loses its price advantage
Old process technology vs advanced 32-
bit processes
Difference in the silicon area of
8-bit vs 32-bit cores shrinks to nothing
16%
17%
60%
6%
1%
13%
19%
58%
7%
3%
16%
18%
61%
4%
1%
18%
19%
54%
6%
2%
8-bit processor
16-bit processor
32-bit processor
64-bit processor
Dont know
2009 (N = 1,533)
2008 (N = 1,067)
2007 (N = 938)
2006 (N = 917)
Questionnaire:
My current embedded project's main processor is
32-bit offers more value for money!
Swamy, IT 10/11/2014
Balanced performance / code density
with ARM & Thumb instruction sets
Cost-effective performance in
embedded systems:
Wide range of peripherals
Low-cost, high-speed memory
implementation
Low power consumption
Supported by huge ecosystem
Why is ARM outgrowing the 32-bit
market?
ARM to be the leading 32-bit MCU
architecture in 2011 (Semicast, 2009)
ARM Connected Community 450+ companies
0
50
100
150
200
250
300
2005 2006 2007 2008 2009
ARM MCUs (Mpcs)
Swamy, IT
10/11/2014
Selection b/w ARM & POWER PC for
SBC
For integration on the chip is important in compact
space ARM.
For high performance defense applications, where
the processing speed is important Power PC.
ARM based SBC is roughly $100 to $300 less than
Intel processor based board.
Example SBC: Beagle Board

Source:EFY August 2010
Swamy, IT 10/11/2014
What is ARM?

The ARM is a 32-bit reduced instruction set
computer (RISC) instruction set architecture
(ISA) developed by ARM.
It was known as the Advanced RISC
Machine, and before that as the Acorn
RISC Machine.
The ARM core is 32 bit general purpose
microprocessor.
ARM's business has always been to sell IP
cores, which licensees use to create
microcontrollers and CPUs based on this
core.

Swamy, IT 10/11/2014
ARM licensees
IP Cores
-Gate Netlist (Hard)
-Synthesizable RTL code (Soft)
With the synthesizable RTL, the customer has
the ability to perform architectural level
optimizations and extensions.
This allows the designer to achieve exotic
design goals not otherwise possible with an
unmodified net list
While ARM does not grant the licensee the right
to resell the ARM architecture itself, licensees
may freely sell manufactured product (chip
devices, evaluation boards, complete systems,
etc.).

Swamy, IT 10/11/2014
Examples: ARM Controllers
AT91C140:
ARM7TDMI. ARM. Thumb. Processor Core
Ethernet Bridge
Dual Ethernet 10/100 Mbps MAC Interface
16-Kbyte Frame Buffer
1K-Byte Boot ROM, Embedding a Boot Program
Enable Application Download from DataFlash.
External Bus Interface
On-chip 32-bit SDRAM Controller
4-Chip Select Static Memory Controller
Multi-level Priority, Individually Maskable, Vectored Interrupt
Controller
Three 16-bit Timer/Counters
Two UARTs with Modem Control Lines
Serial Peripheral Interface (SPI)
48 General-purpose I/O Pins
Swamy, IT 10/11/2014
Digi NET+50:Block Diagram
The Digi NET+50 is a high-performance, highly integrated, 32-bit,
system-on-a-chip ASIC, designed for use in intelligent networked devices
and Internet appliances
Swamy, IT 10/11/2014
TI OMAP

Swamy, IT 10/11/2014
RISC design
The ARM core uses a RISC architecture ?

The RISC design goals
Instructions
-reduced number of instructions
-simple instructions executing in a single cycle.
-Fixed length instructions
-Software support for many instructions
E.g. divide operation repeated subtraction(PIC
16F84)
-Compiler design is complex
-Orthogonal instruction set



Swamy, IT 10/11/2014
Design goals
Pipelines
-Fixed length instructions pipeline design is simpler
-Ideally the pipeline advances one step on each
cycle for maximum throughput

Why instruction queue length of 8086 is 6 bytes only?
Hint: Instruction set architecture


Ans: Variable length instructions:1to 6 bytes
Swamy, IT 10/11/2014
Design goals
Register file
-Large general purpose register set
-Orthogonal instruction set
-no register specific instructions
-Register can be used to store either data or address.
Load-Store Architecture
-Separate load & store instructions transfer data between
the register bank and external memory.

Swamy, IT 10/11/2014
ARM features
The ARM architecture includes the following RISC
features:
Load/store architecture.
No support for misaligned memory accesses (not all
cores)
Uniform 16 32-bit register file.
Fixed instruction width of 32 bits to ease decoding and
pipelining, at the cost of decreased code density.
-Later, "Thumb mode" increased code density.
Mostly single-cycle execution


Swamy, IT 10/11/2014

Conditional execution of most instructions,
reducing branch overhead and compensating
for the lack of a branch predictor.
It avoids branch instructions when generating
code for small if statements
In the C programming language, the loop is:
while (i != j)
{
if (i > j)
i -= j;
else
j -= i;
}



Additional design features
Swamy, IT 10/11/2014
In ARM assembly, the loop is:
loop :CMP Ri, Rj ; set condition "NE" if (i != j), ;
"GT" if (i > j), ;
or "LT" if (i < j)
SUBGT Ri, Ri, Rj ; if "GT" (greater than), i =
i-j; SUBLT Rj, Rj, Ri ; if "LT" (less than), j =
j-i;
BNE loop ; if "NE" (not equal), then
loop
which avoids the branches around the
then and else clauses.
Swamy, IT 10/11/2014
Additional design features
Another feature of the instruction set is the
ability to fold shifts and rotates into the data
processing instructions, for example, the C
statement
a += (j << 2);
could be rendered as a single-word, single-
cycle instruction on the ARM.
ADD Ra, Ra, Rj, LSL #2
This results in the typical ARM program being
denser than expected with fewer memory
accesses; thus the pipeline is used more
efficiently.
Swamy, IT 10/11/2014
Enhanced DSP instructions were added to
standard ARM instruction set to support fast
multiplier operation.
E.g.MLA (Multiply & Accumulate instruction)
Arithmetic instructions alter condition codes
only when desired.
32-bit barrel shifter which can be used
without performance penalty with most
arithmetic instructions and address
calculations.
A link register for fast function calls.
2-priority-level interrupt subsystem with
switched register banks.

Additional design features
Swamy, IT 10/11/2014
Advanced Microcontroller Bus
Architecture (AMBA) has been widely
used for ARM processors.


Additional design features
Swamy, IT 10/11/2014
The architecture provides a non-intrusive
way of extending the instruction set using
"coprocessors .
The coprocessor space is divided logically
into 16 coprocessors .
All ARM peripherals are memory mapped.
-ARM memory space
-Coprocessor memory space
Additional design features
Swamy, IT 10/11/2014
ARM based boards in the department:
Beagle Board-TI OMAP
LPC 111x and LPC 134x-NXP
semiconductors
Freescale I.MX21

Swamy, IT 10/11/2014