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Instruction set
INSTRUCTION SET
Data Handling
Arithmetic
Logic
Data Test
Branch
Jump & Subroutine Calls
MNEMONIC
LOAD ACMLTR
LDAA
LDAB
(M)
(M)
LDD
LDX
LDY
LDS
(M)
(M+1)
LOAD <EA>
OPERATION
A
B
RH
RL
LEAX
<ea>
LEAY
<ea>
LEAS
<ea>
SP
Y
2000
MEM
ACCB
B
X REG
25
2025
STAA
STAB
STD
STX
STY
STS
PUSH DATA
TO STACK
PSHA
PSHB
PSHC
PSHD
PSHX
PSHY
PULA
PULB
PULC
PULD
PULX
PULY
PULL DATA
FROM STACK
MOVE
EXAMPLE:
OPERATION
MNEMONIC
MOV
MOVW
A
B
(M)
(M)
RH
RL
(SP) - 1
( REG)
(M)
(M+1)
SP
M(SP)
(SP) - 2
SP
(RH : RL ) (M(SP) ):(M(SP+1) )
(M(SP) )
REG
(SP) + 1
SP
(M(SP)):(M (SP)+1 )
(SP) + 2
MEM
RH: R L
SP
MEM
2,X+ , 2,-Y
HCS12 Technical Training
Module 3 - Instruction Set, Slide 4
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001.
STACK OPERATION
EXAMPLE:
PSHX
PSHX
BEFORE
AFTER
B7
MEM
B7
B0
MEM
B0
INCREASING
ADDRESSES
SP
$4000
TOP OF STACK
INCREASING
ADDRESSES
SP
SP
SP
$3FFE
$3FFF
$4000
XH
XL
TOP OF STACK
MNEMONIC
OPERATION
TRANSFER DATA
TBA
TAB
B
A
TXS
TYS
SP
TSY
TSX
SP
TFR
EXCHANGE
EXG
EXCHANGE DATA
XGDX
XGDY
A
B
A, B, CCR, D, X, Y, SP
A, B, CCR, D, X, Y, SP
A, B, CCR, D, X, Y, SP
A, B, CCR, D, X, Y, SP
D
D
X
Y
EXAMPLE1: TFR X ,A
EXAMPLE2: EXG Y ,B
FUNCTION
MNEMONIC
OPERATION
DECREMENT
DEC
DECA
DECB
(M)-1
A-1
B-1
DEX
DEY
DES
X-1
Y-1
S-1
INC
INCA
INCB
(M)+1
A+1
B+1
(M)
A
B
INX
INY
INS
X+1
Y+1
S+1
X
Y
S
INCREMENT
(M)
A
B
X
Y
S
FUNCTION
MNEMONIC
OPERATION
COMPLEMENT, 2'S
(NEGATE)
NEG
NEGA
NEGB
0-(M)
0-A
0-B
COMPLEMENT, 1'S
COM
COMA
COMB
(M)
A
B
CLEAR
CLR
CLRA
CLRB
0
0
0
BIT(S) CLEAR
BCLR
(M)
MASK
(M)
BIT(S) SET
BSET
(M) + MASK
(M)
(M)
A
B
(M)
A
B
(M)
A
B
MNEMONIC
MININUM OF TWO
UNSIGNED 8-BIT
VALUE
MININUM OF TWO
UNSIGNED 8-BIT
VALUE
MAXIMUM OF TWO
UNSIGNED 8-BIT
VALUE
MAXIMUM OF TWO
UNSIGNED 8-BIT
VALUE
LOOP
MINA
BHS
OPERATION
MINA
(A)
MINM
(M)
MAXA
(A)
MAXM
(M)
1,X+
LOOP
MNEMONIC
MININUM OF TWO
UNSIGNED 16-BIT
VALUE
MININUM OF TWO
UNSIGNED 16-BIT
VALUE
EMINM
MAXIMUM OF TWO
UNSIGNED 16-BIT
VALUE
MAXIMUM OF TWO
UNSIGNED 8-BIT
VALUE
EMIND
EMAXD
EMAXM
OPERATION
MIN ((D), (M:M+1))
(D)
(D)
MNEMONIC
ROTATE LEFT
ROL
ROLA
ROLB
M
A
B
ROR
RORA
RORB
M
A
B
ASL(LSL)
ASLA(LSLA)
ASLB(LSLB)
ASLD(LSLD)
M
A
B
D
ROTATE RIGHT
SHIFT LEFT,
ARITHMETIC
(LOGICAL)
OPERATION
b7
b7
SHIFT RIGHT,
LOGICAL
ASR
ASRA
ASRB
M
A
B
LSR
LSRA
LSRB
LSRD
M
A
B
D
b0
0
b7
b0
A
SHIFT RIGHT,
ARITHMETIC
b0
b15
b0
b7
b0
0
b7
0
A
b15
b0
b0
FUNCTION
MNEMONIC
TEST
BIT TEST
BITA
BITB
A (M)
B (M)
COMPARE
CBA
CMPA
CMPB
A-B
A-(M)
B-(M)
CPD
CPX
CPY
CPS
R L-(M+1)
R H-(M)-C
COMPARE STACK
TEST, ZERO OR
MINUS
TST
TSTA
TSTB
SP - ( M :M +1)
(M)-0
A-0
B-0
MNEMONIC
CONDITION
CCR TEST
INDICATION
(L) BMI
MINUS
N=1
r=NEGATIVE
(L) BPL
PLUS
N=0
r=POSITIVE
*(L) BVS
OVERFLOW
V=1
r=SIGN ERROR
*(L) BVC
NO OVERFLOW
V=0
r=SIGN OK
*(L)BLT
LESS
[N V]=1
A<M
*(L)BGE
GREATER OR EQUAL
[N V]=0
A >= M
* (L)BLE
LESS OR EQUAL
[Z+(N V)]=1
A <= M
*(L) BGT
GREATER
[Z+(N V)]=0
A>M
(L)BEQ
EQUAL
Z=1
A=M
(L) BNE
NOT EQUAL
Z=0
A <> M
(L)BHI
HIGHER
[C+Z]=0
A>M
(L) BLS
LOWER OR SAME
[C+Z]=1
A <= M
(L)BCC (BHS)
CARRY CLEAR
C=0
A >= M
CARRY SET
C=1
A<M
Indication
refers to the
use of a
CMPA M
instruction
immediately
before the
branch
MNEMONIC
DBEQ
DBNE
IBEQ
IBNE
OPERATION
COUNTER - $01
COUNTER
IF COUNTER =0, THEN (PC)+$0003 +REL
PC
COUNTER - $01,
COUNTER
IF COUNTER <>0, THEN (PC)+$0003 +REL
PC
COUNTER + $01
COUNTER
IF COUNTER =0, THEN (PC)+$0003 +REL
COUNTER + $01
COUNTER
IF COUNTER <>0, THEN (PC)+$0003 +REL
PC
TBEQ
PC
TBNE
PC
EXAMPLE:
LOOP
PC
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001.
BRSET
BRCLR
OCL
(M) MASK SERVICE
OP CODE
OPERAND
MASK
BRANCH DISP.
ADDESSING MODES ALLOWED ARE: DIR, EXT, IDX, IDX1 & IDX2.
EXAMPLE:
WAIT BRCLR PORTD,Y $80, WAIT
HCS12 Technical Training
Module 3 - Instruction Set, Slide 15
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. Motorola, Inc. 2001.
ARITHMETIC INSTRUCTIONS (4 of 4)
FRACTIONAL DIVIDE INSTRUCTION
FRACTIONAL DIVIDE
FDIV
ARITHMETIC INSTRUCTIONS (1 of 4)
FUNCTION
MNEMONIC
OPERATION
ADDA
ADDB
ADDD
A + (M)
A
B + (M)
B
D L + (M+1)
DL; DH + M + C
ADD
ACCUMULATORS
ABA
ABX
ABY
A+B
X+B
Y+B
ADCA
ADCB
A+M+C
B+M+C
DECIMAL ADJUST
DAA
ADD
DH
A
X
Y
A
B
ARITHMETIC INSTRUCTIONS (2 of 4)
FUNCTION
MNEMONIC
OPERATION
SUBTRACT
SUBA
SUBB
SUBD
A (M)
B (M)
D L (M+1)
SUBTRACT
ACCUMULATORS
SBA
SUBTRACT WITH
CARRY
SBCA
SBCB
MULTIPLY
MUL
A B
A
B
DL; DH (M) C
A
A (M) C
B (M) C
A*B
A
B
EXTENDED MULTIPLY
EMUL
D*Y
Y:D
EXTENDED MULTIPLY
SIGNED
EMULS
D*Y
Y: D
DH
ARITHMETIC INSTRUCTIONS (3 of 4)
DIVIDE INSTRUCTIONS
OPERATION
D REG / X REG
RESULT
QUOTIENT IS IN X
REMAINDER IS IN D
INTEGER DIVIDE
IDIV/IDIVS
EDIV EXAMPLE:
OPERATION
EDIV/EDIVS
EDIV[ S ]
(Y:D)/ (X)
Y; REMAINDER
OPERATION:
15
M ~ M+3
15
EXAMPLE:
EMACS
$2500
(* 32-BIT RESULT *)
LOGIC INSTRUCTIONS
FUNCTION
MNEMONIC
AND
ANDA
ANDB
ANDCC
A (M) A
B (M) B
CCR MASK
EXCLUSIVE OR
EORA
EORB
A
B
INCLUSIVE OR
ORAA
ORAB
A + (M)
B + (M)
ORCC
OPERATION
(M)
(M)
CCR
A
B
A
B
CCR + MASK
CCR
FUNCTION
MNEMONIC
OPERATION/BRANCH TEST
NO OPERATION
NOP
JUMP TO ADDRESS
JMP
(M)
PC H , (M+1)
PC L
JUMP TO SUBROUTINE
JSR
PC L
PC H
(M)
(M SP ), SP-1
(M SP ), SP-1
PC H , (M+1)
SP
SP
PC L
RTS
BRANCH TO SUBRTN
BRANCH ALWAYS
BRANCH NEVER
SP+1
SP+1
SP,(M
SP,(M
BSR
PC L
PC H
(M)
BRA
BRN
NO TEST
NO TEST, PC
SP )
SP )
(M SP ), SP-1
(M SP ), SP-1
PC H , (M+1)
PC
PC
H
L
SP
SP
PC
NEXT INST.
FUNCTION
CLEAR CARRY
CLEAR INTERRUPT MASK
CLEAR OVERFLOW
SET CARRY
SET INTERRUPT MASK
SET OVERFLOW
ACCUMULATOR A
CCR
CCR
ACCUMULATOR A
MNEMONIC
CLC
CLI
CLV
SEC
SEI
SEV
TAP
TPA
OPERATION
0
C
0
I
0
V
1
C
1
I
1
V
A
CCR
CCR
A
OR CONDITION CODE
ORCC
CCR + OPERAND
ANDCC
CCR ^ OPERAND
FCC
FCB
ORG
$5000
DATA TO MOVE
0
$4000
LOOP
BEQ
DONE
DONE
BRA
LOOP
BRA
DONE
8. GO TO STEP 3.
9. STAY HERE.
Write a routine to clear the HCS12 RAM memory, assume RAM begins at $5000
and ends at $5FFF.