May 16, 2000

USB 2.0
Hub Additions
John Garney
Hub Working Group Chair
Intel Corporation

May 16, 2000

Hub Additions
Requirements and Architecture
Additions to USB1.1

Transaction Translator
Bulk/Control Transaction Handling
Isochronous/Interrupt Transaction Handling

Additions to Chapter 11

May 16, 2000

Requirements:
Provide high-speed expansion
Isolate full/low-speed from high-speed
Avoid lower speed impact on HS, i.e., LS impact on FS

All USB2.0 Hub Ports support HS/FS/LS

Optional: standardized port indicators (LEDs)

May 16, 2000

Hub In High Speed System

Client Driver

Client Driver

System SW
USB 2.0 Host
Controller

High Speed Only

HS Hub

USB 1.1
Device
USB 1.1 Hub

HS Device

Full/Low Speed

USB 1.1
Device

(2 x 12Mb/s
Capacity)

Hub provides high-speed expansion (ala 1.1 hub)

Hub provides additional classic bus(es)
Same total number of devices per USB2.0 Host Controller (e.g. 127)

Greater end user value than classic hub

Performance, expansion and ease of use

Hub is user selected device (not required for all systems)

May 16, 2000

Hub Classic Pieces

High Speed Only
Port

HS/Classic
Hub
Repeater

Repeater

Port

HS/Classic
Hub State
Machine

Port

HS/Classic
Hub
Controller

Port

High speed signaling

Also, FS/LS signaling for 1.1 compatibility

Reclocking

State Machine
HS termination sequencing
HS Detect, Reset, Suspend, Resume

Hub Controller

Respond to hub device class requests/events

May 16, 2000

Hub Architecture
High Speed Only
Port

Full/Low
Speed

HS/Classic
Hub
Repeater

Transaction
Translator

HS/Classic
Hub State
Machine

HS/Classic
Hub
Controller

Routing Logic
Port

Port

.....

Port

Same as classic hub:

High & full/low-speed repeaters, determined by upstream facing link
Hub controller
No different then classic USB besides high-speed signaling

Minor changes from classic hub:

Hub state machine (HS detect, HS termination transitions, test mode)

New in hub:
Transaction Translator
Routing logic
May 16, 2000

Hub New Pieces

High Speed Only
Port

Full/Low
Speed

Repeater, Controller, ...

Transaction
Translator

Routing Logic
Port

Port

.....

Port

Port Routing Logic

Controllable electrical connection between:
Full/Low (Transaction Translator), or
High-Speed (Repeater)

Route done once per device reset

Transaction Translator
Major addition for USB 2.0
Uses split transaction protocol HC support
May 16, 2000

Host Controller / TT Interactions

Host
1 SPLIT-s, OUT, DATAx
(Start-split)

TT

6 - ,ACK
5 SPLIT-c, OUT,

(Complete-split)

4 - ...,ACK

3 - OUT, DATAx, ...

Device

Interrupt
Out
Example

Host Controller issues start-split transaction to TT

TT buffers full/low speed transaction information (X) locally

TT issues full/low speed transaction on downstream bus
TT buffers full/low speed transaction results (R) locally

May 16, 2000

Host Controller issues complete-split transaction to TT

TT responds with results

Transaction Translator Overview

Transaction Translator
Bulk &
Control

Interrupt &
Isochronous

Two separate portions to Transaction Translator

Bulk/Control support
Interrupt/Isochronous support

Bulk/Control uses USB flow control to make progress

PING not used

Interrupt/Isochronous uses a scheduled full/low speed

transaction pipeline
Separate buffers are used for each TT portion
May 16, 2000

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TT Bulk / Control
High Speed Start-/Complete-Split

TT
Bulk/Ctrl #1

Bulk/Ctrl #2

Full/Low Speed Transaction

TT buffers 2 or more bulk/control transactions

TT issues full/low speed transaction when no periodic
transactions pending
Host controller issues split transactions to TT
Allows starting/completing full/low-speed transactions each microframe
Normal approach of bandwidth reclamation is used
Tries to issue HS start-split; if successful, next attempt does complete-split
May 16, 2000

11

TT Int. / Isoch. Pipeline

High Speed Start-Split

TT

High Speed Complete-Split

Start
Handler

Complete
Handler

Start-split Complete-split
FIFO
FIFO
Full/Low
Handler

Host software budgets when full/low-speed transaction will run

Host schedules start-split before earliest start time
Host schedules complete-split at latest finish times
Scheduling accounts for variation due to bit-stuffing
and timeouts, etc.
May 16, 2000

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Example: Int. OUT Split Trans.

6 - ,ACK
5 SPLIT-c, OUT, ...

1 SPLIT-s, OUT, DATAx

TT
2

Start
Handler

Complete
Handler

Start-split
FIFO

Complete-split
FIFO

Full/Low
Handler

3 - OUT, DATAx, ...

May 16, 2000

4 - ...,ACK

Host Controller issues start-split transaction to TT

TT buffers full/low speed transaction information locally
TT issues full/low speed transaction on downstream bus
TT buffers full/low speed transaction results locally
Host Controller issues complete-split transaction to TT
TT responds with results

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Hub Cost / Complexity

Estimate
Port

TT FIFOs
TT Logic

High-Speed Classic Hub

Routing Logic

Port

Port

Port

Classic Hub + new things

Classic Hub - implementation dependent, but knowable baseline
New things
Signaling
Required for any High-Speed device
Logic (routing, TT)
RAM (buffer space, transaction pipeline)

Total (approximate)
40KGates + 1800 Bytes with 4 downstream ports
28KGates + (3KG * # of downstream ports) + 1800 Bytes
May 16, 2000

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USB2.0 Hub
Additions Summary
Hub Ports Support all Speeds (High/Full/Low)
Isolation of High and Full/Low Speeds via TT
Simultaneous High and Full/Low-Speed Transactions

Full/Low Speed (12Mb/s) bus per TT

Can be TT per hub or TT per port

TT Internals Overview
Bulk/Control buffering
Interrupt/Isochronous scheduled pipeline

May 16, 2000

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