Differential Signaling

Differential Signaling
Introduction
Reading Chapter 6
12/4/2002
Agenda
Differential Signaling Definition

Voltage Parameters
Common mode parameters
Differential mode parameters
Current mode logic (CML) buffer

Relate to parameters
Modeling & simulation
Timing parameters
Clock recovery
Embedded clock
AC coupling
Common mode response

Issues with simulation
8B10B encoding
DC balanced codes
Duty Cycle distortion

Cycle
12/4/2002
Single Ended Signaling

All electrical signal circuits require a loop or return
path.
Single ended signal subject several means of
distortions and noise.
Ground or reference may move due to switching currents

(SSO noise). We touched on this in the ground conundrum
class.
A single ended receiver only cares about a voltage that is
referenced to its own ground.
Electromagnetic interference can impose voltage on a
single ended signal.
Signal passing from one board to another are subject to
the local ground disturbance.
We can counteract many of these effect by adding
more ground.
As frequencies increase beyond 1GHz, 80% of the
signal will be lost.
12/4/2002
Review of threshold sensitivity

Vref
Vref
Vref
Vss Tx
Short line
Long line
The wave is referenced to either Vcc or Vss.
Vss Rx1
Vss Rx2
Consequently the effective DC value of the wave will

be tied to one of these rails.
The wave is attenuated around the effective DC
component of the waveform, but the reference does
not change accordingly. Hence the clock trigger point
between various clock load points is very sensitive to
distortion and attenuation.
12/4/2002
Any signal can be considered a loop is completed by two wires.
One of the wires in single ended signaling is the ground plane
Differential signaling uses two conductors
The transmitter translates the single input signal into a pair

of outputs that are driven 180 out of phase.
The receiver, a differential amplifier, recovers the signal as the difference
in the voltages on the two lines.
Advantages of differential signaling can be summed up as follows
Differential Signaling is not sensitive to SSO noise.

A differential receiver is tolerant of its ground moving around.
If each wire of pair is on close proximity of one and other. electromagnetic
interference imposes the same voltage on both signals. The difference
cancels out the effect.
Since the AC currents in the wires are equal but opposite and proximal,
radiated EMI is reduced.
Signals passing from one board to another are not subject to the local ground
disturbances.
As frequencies increase beyond 1GHz, up to 80% of the signal may be lost,
but difference still crosses 0 volts.
There are still loss issues for differential signaling but only come into play in high
loss system. Most single ended systems assume approximately 15% channel loss.
12/4/2002
Differential Signaling - Cons
The cost is doubling the signal wires,
but this may not be so bad as compared

to adding grounds to improve single
ended signaling.
Routing constraint: Pair signals need to
be routed together.
Differential signal have certain
symmetry requirements that may pose
routing challenges.
12/4/2002
Differential Signal Parameters

Line 1
Line 2
Voltage on line 1 = a
Voltage on line 2 = b
Differential voltage d = a-b
Common mode voltage c= (a+b)/2
Odd mode signal, o = (a-b)/2
Even mode signal, e = (a+b)/2
Signal on line 1 a = e+o
Signal on line 2 b = e-o
Useful relations; o = d/2; e = c
Reference
12/4/2002
Propagation Terms to Consider
Differential mode propagation

Common mode propagation
Single ended mode (uncoupled)
propagation
This is when the other line is not driven

but terminated to absorbed reflections.
Transmission line matrixes will reflect

these modes.
12/4/2002
Differential Microstrip Example

-9 henry
L11 6.598000
10
-9 henry
L21 1.291000
10
in
-12 farad
C11 4.177000
10
Transmission
line
Zdiff 2
Zcomm
Zse
L11 L21
C11 C21
L11 L21
C11 C21
L11
C11
in
in
-13 farad
C21 6.690000
10
L11 L21
L12 L22
in
L12 L21
L22 L11
C12 C21
C22 C11
C11 C21
C12 C22
inductance and
capacitance matrixes
Zdiff 66.185
ns
Sd ( L11 L21) ( C11 C21) Sd 1.924
ft
Zcomm 47.422
ns
Sc ( L11 L21) ( C11 C21) Sc 1.996
ft
Zse 39.744
Sse L11 C11
Z0 Zse
ns
Sse 1.992
ft
SE: single ended = uncoupled

12/4/2002
10
Differential Impedance
Coupling between lines in a pair always

decreases differential impedance
Differential impedance is always less
that 2 times the uncoupled impedance
Differential impedance of uncoupled
lines is 2 times the uncoupled
impedance.
12/4/2002
Propagation Velocities
11
For TEM structures, (striplines)
Differential mode, Common Mode, and

single ended velocities are the same
For Non TEM and Quasi-TEM structures

(microstrip)
Differential mode, Common Mode, and

single ended velocities and impedances are
not the same.
Common mode can be converted to
differential mode at a receiver and result
in a differential signal disturbance.
12/4/2002
12
Example of Common Mode
Line 1 and line 2 have the same DC offset.

This is DC common mode.
It can be defined as an average DC for time
duration of many UI cycles value as well.
Line1 and line 2 have the same AC offset

This is AC common mode
AC common mode also result from time
differences (skew) between signal on line 1

and line 2. This can result in AC common mode
and differential signal loss.
The following slide will be used to clarify the
above
12/4/2002
Differential Signaling Basics
13
Voltages a and b are respective of signals on lines 1 and 2

We will use a 1GHz sine wave for the signal and offset defined below
ti 1
offseti .9 mod
.2
ns
f
ns
ai sin 2 f ti offseti
ramp wave centered around 1
bi sin 2 f ti offseti
For long channels, at GHz frequencies, signal

tend look like sine waves.
The artificial offset common to line 1 and 2
has an average of 1 and varies around that
average by +/-0.1 in a period manor.
12/4/2002
14
Individual signals
Plot individual line voltages and offset voltage
3
2.33
ai
1.67
bi
offset i 0.33
0.33
1
0.83
1.67
2.5
3.33
4.17
ti
ns
Devices need to have enough common mode dynamic voltage range

to receive or transmit the waveforms. In this case the signals
swing between -0.1 and 2.1.
The sine wave amplitude is 1 and peak to peak is 2.
Signal a and b is what would be observed with 2 oscilloscope
probes
12/4/2002
15
Differential Mode Signal

Plot Differential voltage
2
1
ab
0
1
2
0.83
1.67
2.5
3.33
4.17
t
ns
The differential amplitude is 2 and peak to peak is 4

which is 2 times the individual signal peak to peak
amplitude.
Notice the distortions are gone.
12/4/2002
16
Common Mode Signal

Plot common mode voltage
1.1
aibi
2
1
0.9
0.8
ti
ns
The DC common mode signal is 1

The AC common mode signal is .2 v peak to peak
Some may specifications may call this 0.1 v peak from the DC
average
We will add this common mode to the signals a and b

12/4/2002
Add 150 ps skew to signal b
17
Plot individual line voltages and offset voltage

3
2.33
ai
1.67
bi
offset i 0.33
0.33
1
0.83
1.67
2.5
3.33
4.17
ti
ns
Waveforms do not look so good.

We even have what appears to be non-monotonic
behavior.
12/4/2002
18
Differential signal looks OK

Plot Differential voltage
2
1
ab
0
1
2
0.83
1.67
2.5
t
ns
3.33
4.17
max( a b) min ( a b) 3.562
However we lost differential signal
amplitude.
It used to be 4 peak to peak and now is
3.562.
12/4/2002
Common mode measurements are different

Plot common mode voltage
2
aibi
1.5
1
0.5
a
2
mean
ns
a
2
max
ti
a
2
max mean
a
2
max
a
2
mean
a b 0.944
min
a
2
min
b
0.504
Average is still 1. Peak to peak is 0.944 but peak is 0.504

AC common mode signals can be converted to differential
12/4/2002
19
20
PWB structures that introduce Skew

An escape
from a BGA or
connector pins
introduces
skew
This is an
example of
skew
compensation
12/4/2002
Bends introduce skew
21
Back to back
bends
compensate for
skew from
frequencies
below 2 GHz.
12/4/2002
22
More Terms: Balanced and Unbalanced
Good Agilent Technologies article on balance

and unbalanced signaling
http://we.home.agilent.com/upload/cmc_upload/t
mo/downloads/EPSG084733.pdf
Unbalanced signaling in reference to ground

Balanced signaling is referenced only to the
other port terminal.
If each channel is identical, then this suggests a

virtual AC ground between the two terminals. It
is often useful to allow this AC ground to be a DC
voltage to biasing devices.
12/4/2002
23
Ethernet 10/100BASE-T example

Filter
50
Transformer
50 TP1
50
TN1
50
Commonmode choke
Unbalanced
Balanced
12/4/2002
Low Voltage Differential Signaling: LVDS
200MHz 500 MHz Range

Published by IEEE in 1995
Lacks robustness for GHz Signaling
Well suite distributing system clocks
Good noise margin
Common mode impedance has wide range provide
buffer design flexibility
Differential impedance is optimize around 100
Differential receiver switching thresholds are
tighter than for single ended logic.
Most device require external termination and bias
resistors
Does not have capacitance or package spec. This
severely limits GHz operation
12/4/2002
24
Current Mode Logic
25
Emerging technology
No real spec yet but can infer operation from
specs like PCI Express , Infiniband, USB,
SATA, etc.
Tx and Rx lines are separate
The Tx driver steers current between the
differential terminals
AC coupling between Tx and Rx with a
series capacitor provides common mode
design flexibility
Termination is in buffers. This may require
compensation or a band gap reference to
insure a tight resistance range.
12/4/2002
Example of Simple CML Differential Behavioral Circuit

This exponent
determines wave
shape
Data Waves
1
3 per
pulse ( t )
ns
wave ( t) 1 e
0.5
Data Pulses
10
Wavep ( t)
Wavep ( t) 1
20
10
20
Vcc
30
Balance
between for
FET switch
I_source
30
Waven ( t t d) 1
r_termn balancep
Waven ( t t d)
r_termp,
C_term
Positive
Terminal
Negative
Terminal
Vss
r_termn balancen
This switch
time offset
r_termn,
C_term
12/4/2002
26
27
Example of Sensitivities: I, balance, C
Vcc
I_source
More prominent
for faster edges
12/4/2002
28
Example of Sensitivities: Slew, Skew, R
Vcc
I_source
R/F slew
+/skew
12/4/2002
29
Serial Differential
GHz transmission will have many UIs of

data in transit on the interconnect at
any points in time.
Hence it becomes useful to think of
this as serial data transmission.
Often multiple single channels are
ganged in parallel to achieve even
higher data throughput.
12/4/2002
30
AC coupling issues
Series capacitors can build up charge

difference between differential
terminals for the following reasons.
Unequal numbers of zero and ones
Duty cycle (UI) distortion.
The solution is to use a data code that

is DC balanced.
8B10B (8 bit 10 bit) with disparity is one

such code
Tight UI control is a basic requirement

for keeping the signal eye open
12/4/2002
Eye Diagram
31
The eye diagram is a convenient way to represent
what a receiver will see as well as specifying

characteristics of a transmitter.
The eye diagram maps all UI intervals on top of one
and other.
The opening in eye diagram is measure of signal
quality.
This is the simplest type of eye diagram. The are
other form which we will discuss later
Eye Diagram
12/4/2002
32
Creating eye diagram
Plot periodic voltage time ramps (saw
tooth waves) on x verses the voltage

wave on Y.
Can be done with Avanwaves
expression calculator and can be saved
in a configuration file.
12/4/2002
Create ramp with expression builder

Start of
relative eye
position
Unit Interval
Time of eye
start
12/4/2002
33
Copy Ramp to X Axis
34
Use middle button to drag ramp to

Current X-Axis
12/4/2002
35
Voltage and period volt-time ramp
12/4/2002
Clocking
36
The one thing omitted in the suggests in the
previous slides on eye diagrams was the chop

frequency.
We assumed it was UI. This is simple for
simulation. Time marches along and all signals
start out synchronized in time. This is not
true for real measurement since edges will
significantly jitter and make it difficult to
determinate where the exact UI is positioned.
Presently, there are basically two forms of
GHz+ clocking
Embedded clocking
Forwarded clocking
12/4/2002
Embedded clocking
37
This what is used in Fiber Channel, Gigabit

Ethernet, PCI Express, Infiniband, SATA,
USB, etc.
The clock is extracted from the data
There is requirement that data transitions are at

a minimum rate. 8B/10B guarantees this. We
discuss this in more detail later.
A phase interpolator is normally used to extract
the clock from the data. We discussed the phase
interpolator in the clocking class. The phase
interpolator is tied to the PCI Express-like jitter
spec: Median and Jitter outlier.
12/4/2002
38
Jitter Median and Outlier Spec

Eye opening is defined from a stable UI.
Jitter median used to determine a stable UI
It is used as a reference to determine eye opening
Jitter Outlier is used to guarantee limits of

operation
UI
Jitter outlier
Jitter Median
Eye diagram
12/4/2002
Forwarded Clocking
39
The Tx clock is sourced and received down
stream. The clock is a Tx data buffer

synchronized with the Tx data bits.
A synchronization or training sequence on a
data line is used to adjust the receiver clock
so that it is in phase synchronization with the
data.
The caveat is that the actual data clock lags
the real data by a few cycles.
The whole idea is that the jitter introduced
over these cycles would be smaller than the
jitter associated with two the PLLs used to
provide base clocks for an embedded clock
design.
12/4/2002
40
Aspects of AC coupling
We will explore issues with AC coupling with a

simulation example.
First we will create a simple CML differential
model
Next we will tie it to a differential
transmission line and a terminator.
Assignment 7 is to reproduce these effects
with a HSPICE program. The output
Avanwaves with a power point story summary
what you will hand in.
The basis for our work will be last semesters
testckt.sp deck
12/4/2002
41
Behavioral Data Model Example

12 bit of repeating data
010101 001001 v(t) data

UI = 500 ps
Tr=Tf=100ps
Wave shape*
( v ( t )*2.4 ) 2.5
1 e
Rterm=50
Vswing = 800 mV
Cterm=0.25pf
I=Vswing/(50||50)/2
* Refer to first course
12/4/2002
42
AC coupled Differential Circuit

Vcc
AC coupling caps are

normally larger, but
are scaled down to
illustrate common
mode effects
16ma
0 0/800mV
to 1V
VCR
1.0gHz
VCR
.25pf
50
.25pf
10n
.25pf
1nH
50
1nH
50
50
1nH
1nH
10n
.25pf
12/4/2002
43
Top Level HSPICE CODE
Modified
Convenience
12/4/2002
No initial conditions on DC blocking caps
300 ns of simulation time!

Cblkn pkg2_nb pkg2_n 1nf $ic=400mv
Cblkp pkg2_pb pkg2_p 1nf $ic=400mv
101010 101010 repeating 12 bit pattern
Reproduce this at
package 2 (receiver)
Differential
Single ended
12/4/2002
44
Set IC to Vswing/2
45
Reproduce this at
Differential
Single ended
12/4/2002
Not completely fixed
46
Initial voltage for D+ and D+ is not 0 so

there is a step response when the wave
reaches the receiver.
We can fix this by multiplying both n
and p control waves for the VCR
(voltage controlled resistor) by 0 for
the first cycle.
This forces the DC solution at the other
end of the line to 0 volts differential.
12/4/2002
47
Insure both legs start at same voltage

Qualifying voltage
Qualifying voltage
n control voltage
Qualifying voltage
p control voltage
12/4/2002
Results Pretty good

May have to ignore
48
Reproduce this at
first 1-2 cycles
Differential
Single ended
12/4/2002
Now lets change bit pattern
49
Reproduce this at
100000001010
The pattern creates a DC charge to be built up in the
cap
The solution is to create a code that has equal
amount of 1s and zeros. This is the rational for 8bit
10 bit (8b10b) coding
Differential
Single ended
12/4/2002
50
Crossing Offset
The crossing offset is the horizontal
line that is in the vertical center of the

eye and it should be at 0 volts for a
differential signal.
The amount of offset is the average DC
value. A simple approximation is one
minus the ratio of ones to zeros times
the received vswing/2.
This does not included edge shape effects
12/4/2002
51
Repeat patterns of 5 ones and 6 zeros

Approx. offset
483
5
1 40.25
2
6
Reproduce this at
Hint:
start eye
diagram
at 200 ns
12/4/2002
8b/10b encoding and background

Courtesy of
Scott Gardiner, Intel
12/4/2002
53
8b/10b - Simple Scheme
The encoding is comprehended in a set

of tables which conform to a set of
predetermined rules
Helpful Hint: Complete tables that give all

the literal 10b encodings do exist- and they
comprehend all of the encoding rules
8 bits are encoded into 10 bits
12/4/2002
54
8b/10b: Overview
The 10 bits are referred to as a symbol or a code
group:
The original 8 bits are broken into a 3 bit block and a
5 bit block (each of these are called sub-blocks)
F1 111
10001
The 3 bit sub-block (labeled HGF) is encoded into 4
new bits (labeled fghj) & the 5 bit sub-block (EDCBA)

is encoded into 6 new bits (abcdei)
HGFEDCBA notation commonly represents the un-encoded
bits, and abcdeifghj represents the encoded bits; note
that the relative order and position of the sub-blocks is
switched upon encoding
HGF
EDCBA abcdei
fghj
Hence, an extra bit, j , is added to the newly encoded 3 bit

block and an extra bit, i , to the encoded 4 bit block creating
a 4 and 5 bit sub-blocks
12/4/2002
8b/10b Character Conventions
55
Both Data Characters and Special Control

Characters exist; (nomenclature: D.a.b &
K.a.b)
D/K = Signifies Data or Control
a = 5 bit block to be encoded
b = 3 bit block to be encoded
Set of Available Data and Control

Characters
Data (D.a.b)
D0.0-D31.0, D0.1-D031.1, .... D0.7 D31.7

All 256 Possible 8-bit Data characters (00 through
FF HEX)
Control (K.a.b)
K28.0 K28.7, K23.7, K27.7, K29.7, K30.7

12/4/2002
56
8b/10b - DC balancing & Disparity
Never more than 5 consecutive 1s or 0s
allowed in a row (consecutively)..i.e. the

maximum run rate is 5 to maintain a DC
balanced transmission.
This guarantees the lowest frequency to
be 1/10 of the max frequency. i.e. only 1
decade data bandwidth required.
With 8b/10b, either positive (RD+) or
negative (RD-) disparity encoding is
possible
12/4/2002
8b/10b - Disparity
57
Disparity is the difference between the
number of ones and zeros...positive and

negative disparity refer to an excess of ones
or zeros respectively.
Note: neutral disparity is said to occur when
RD+ and RD- encoding are identical- meaning
they will each have the same number of ones
and zeros (there are some exceptions)
A given sub-block or symbol can have an actual
disparity number of either a zero (neutral), +2

or 2, though the Running Disparity is said only
to be Positive, Negative or Neutral.
12/4/2002
8b/10b Running Disparity
58
The Running or Current Disparity (a
binary value of + or -) is tracked by the

TX/RX and is computed at every subblock boundary and at each symbol
boundary.
The value from one sub-block or symbol
is used with that of the next sub-block
or symbol to give a running or
current status.
12/4/2002
8b/10b Running Disparity Algorithm

For a given encoding of a byte, the starting disparity
is what existed at the end of the previous symbol

The running disparity is then calculated first for the
6 bit sub-block, comprehending the starting
disparity value;
The 6 bit sub block disparity value is then used as
the starting disparity when the running disparity
calculated for the 4 bit sub-block
The running disparity for the entire 10 bit symbol is
now the same as the running disparity found at the
end of the 4 bit sub-block (and the running
disparity at the beginning of the next symbol / 6 bit
sub-block is the same as that found at the end of
the this symbol)
Again, a given sub-block or symbol can have an actual
disparity number of either a zero (neutral), +2 or 2,
though the Running Disparity is only said to be
Positive, Negative or Neutral.
12/4/2002
59
60
8b/10b - Running Disparity Calculation Algorithm:
Assumptions: The 8b to 10b encoding has
already been done; A current disparity value is

already assumed
Process: Calculate the disparity for the
leftmost 6 bits first, keeping in mind the
current disparity value before entering the
algorithm. Then calculate the disparity for the
rightmost 4 bits keeping in mind the disparity
value determined after analyzing the previous 6
bits. The disparity for both the 6-bit and the
4-bit blocks should be calculated as follows:
12/4/2002
8b/10b - Running Disparity Calculation Method

Method:
If # of 1s > 0s
Disparity = Positive (1)
Note: Assuming a encoding, more
1s across the entire 10b code
Else if # of 0s > 1s
yields positive
Disparity = Negative (0)
disparity, more 0s yields negative
Else if 6-bit = 000111
disparity, and even #s of 1s and
0s yields neutral disparity
Then Disparity = Positive (1)
(i.e. disparity is the same as it was
before).
Then Disparity = Negative (0)
Then Disparity = Positive (1)
Then Disparity = Negative (0)
Else Disparity = Disparity (if none of the above, then the disparity
value doesnt change)
12/4/2002
61
8b/10b - Disparity & Encoding Example:

Transmitter keeps running track of current
disparity (it is either RD, RD+ or neutral)
Neutral means the disparity tracker keeps the

previous RD- or RD+ value
A Running Disparity of RD+ is always followed

by an RD- encoding and vice versa
If Running Disparity is RD+, the following is

encoded for the data byte F1:
HGF EDCBA abcdei fghj
111 10001 100011 0111 (RD- encoding)
If Running Disparity is RD-, the following is
encoded for the data byte F1:
HGF EDCBA abcdei fghj
111 10001 100011 0001 (RD+ encoding)
12/4/2002
62
63
8b/10b - Disparity & Encoding Example:

Note that the number of ones and zeros in the
currently chosen encoding works to balance out the

offset in the number of ones and zeroes (tracked by
the Running Disparity value) from the previous
encoding
I.E. : Dont confuse the definition of Positive Disparity with
the RD+ encoding choice!
Positive Disparity means there is a current running total of
more ones than zeros!
Thus, an RD+ encoding generally has more zeros than ones!
Also note that it is possible that the 4-bit sub-block
of a RD- or RD+ symbol encoding can yield a negative

or positive disparity, respectively thus forcing more
than one RD- encoding to be used consecutively
12/4/2002
Summary: Example conversion
64
HEX Data Byte (8b) to be Encoded
OR
F1
Binary Data Byte (8b) to be Encoded
1111 0001
10b Encoded symbol (RD-)
100011 0111
10b Encoded symbol (RD+)

100011 0001
12/4/2002
65
Possible Patterns
Repeating Comma [K28.5] Pattern (RD- followed by
RD+):
001111 1010 110000 0101 001111 1010 110000 0101
(RD-)
(RD+)
(RD-)
(RD+)
6 bit encoding starts with an RD- and uses an positive
disparity encoding.6 bits encoding yields an RD+..4-bit
encoding starts with a RD +4-bit encoding picks a negative
(or neutral encoding) and thus yields a neutral and thus
keeps the RD+. Checks out.
Low Frequency Pattern?? (D30.0 (RD- followed by

RD-)
011110 0100 011110 0100 011110 0100 011110 0100

(RD-)
(RD-)
(RD-)
(RD-)
(RD+)
(RD+)
(RD+)
(RD+)
100001 1011 100001 1011 100001 1011 100001 1011
12/4/2002
66
Possible Patterns
High transition density/frequency pattern:
D21.5 (RD- followed by RD+)

101010 1010 101010 1010 101010 1010 101010 1010
(RD-)
(RD+)
(RD-)
Low transition density pattern:
(RD+)
K28.7 (RD-) & D24.3 (RD+) (although K28.7 is reserved....)

001111 1000 001111 1000 001100 1100 001111 1000 001100 1100
(RD-)
(RD+)
(RD-)
(RD+)
D24.6 (RD-) & D24.6 (RD+)

1100110110 0011000110 1100110110 0011000110
(RD-)
Composite pattern:
(RD+)
(RD-)
(RD+)
D30.7 (RD-) & D13.7 (RD-)

011110 0001 101100 1000 011110 0001 101100 1000
(RD-)
(RD-)
(RD-)
(RD-)
12/4/2002
References
67
Infiniband Architecture Release Specification 1.0

October 24, 2000, Volume 2, Section 5.2x (beginning with page 66)
Franaszek & Widmer (IBM) Patent # 4,486,739

December 4, 1984, Byte Oriented DC Balanced 8B/10B Partitioned
Block Transmission Code
3GIO Architecture Specification- Key Developer Draft

August 21, 2001, Appendix C, pg148-154
ANSI X3.230-1994, clause 11 (and also IEEE 802.3z, 36.2.4).
12/4/2002
68
Other sources of common mode

A DC voltage will build up across the blocking
capacitor if the charge and discharge is not equal.

We have see this can happen if the number of bits is
unbalance.
Another source of imbalance is possible if the duty
cycle of the one and zeros is not 50%.
This can happen in two ways
The time for a one differs from that of a zero. This can be
caused by edge jitter.
The rising time and falling time are miss matched
On the next slide we will take our example with
101010101010 pattern and change the rise time to 50 ps
and fall time to 150 ps for the single ended signals
12/4/2002
69
CM offset from tr/tf mismatch
Reproduce this at
12/4/2002

Differential Signaling

Enviado por

Dados do documento

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Differential Signaling

Enviado por

Direitos autorais:

Formatos disponíveis

Differential Signaling

Differential Signaling Definition

Current mode logic (CML) buffer

Common mode response

Duty Cycle distortion

Single Ended Signaling

Ground or reference may move due to switching currents

We can counteract many of these effect by adding

Review of threshold sensitivity

The wave is referenced to either Vcc or Vss.

Consequently the effective DC value of the wave will

The transmitter translates the single input signal into a pair

Advantages of differential signaling can be summed up as follows

Differential Signaling is not sensitive to SSO noise.

Differential Signaling - Cons

The cost is doubling the signal wires,

but this may not be so bad as compared

Differential Signal Parameters

Propagation Terms to Consider

Differential mode propagation

This is when the other line is not driven

Transmission line matrixes will reflect

Differential Microstrip Example

Sse L11 C11

SE: single ended = uncoupled

Coupling between lines in a pair always

For TEM structures, (striplines)

Differential mode, Common Mode, and

For Non TEM and Quasi-TEM structures

Differential mode, Common Mode, and

Example of Common Mode

Line 1 and line 2 have the same DC offset.

Line1 and line 2 have the same AC offset

differences (skew) between signal on line 1

Differential Signaling Basics

Voltages a and b are respective of signals on lines 1 and 2

ramp wave centered around 1

For long channels, at GHz frequencies, signal

Devices need to have enough common mode dynamic voltage range

Differential Mode Signal

The differential amplitude is 2 and peak to peak is 4

Common Mode Signal

The DC common mode signal is 1

We will add this common mode to the signals a and b

Add 150 ps skew to signal b

Plot individual line voltages and offset voltage

Waveforms do not look so good.

Differential signal looks OK

max( a b) min ( a b) 3.562

However we lost differential signal

Common mode measurements are different

Average is still 1. Peak to peak is 0.944 but peak is 0.504

PWB structures that introduce Skew

Bends introduce skew

More Terms: Balanced and Unbalanced

Good Agilent Technologies article on balance

Unbalanced signaling in reference to ground

If each channel is identical, then this suggests a

Ethernet 10/100BASE-T example

Low Voltage Differential Signaling: LVDS

200MHz 500 MHz Range

Current Mode Logic

Example of Simple CML Differential Behavioral Circuit

Example of Sensitivities: I, balance, C