EECS 465: Digital Systems Design

Lecture Notes
Logic Design Using Compound Components: Multiplexers
SHANTANU DUTT
Department of Electrical and Computer Science
University of Illinois, Chicago
Phone: (312) 355-1314; e-mail: dutt@eecs.uic.edu
URL: http://www.eecs.uic.edu/~dutt
1

The World of Integrated Circuits (LSI/VLSI)

Full-Custom
ASICs

Semi-Custom
ASICs

Simple
Complex
gates (nand/ gates/cells
nor/xor/xnor..)

Muxes

User
Programmable
PLA/PAL
(layout aspect; not
programmable)

PLD
PLA/PAL

FPGA
CPLDs
2

Logic Design Using Multiplexers

A Transmission Gate ( T-Gate )
A
Out

Steering gate.

In=B
A
When A=1, In is Steered to Out.
[I.e., the T-gate conducts]
Thus Out = B when A=1
A
Out = AB
In
Out
Symbolic for T-gate:
A
A is the control input (CI)
T-gate conducts
Normal CI connected to A
Bubbled CI connected to A when A=1.

Reversing the connection of A: A

A
A
In
Out

bubble CI
normal CI

A
T-gate conducts when A=0.
Multiplexer (MUX) Design:
S
Out
I0
Z
S
S

I1

Out

S
Z= I0 when S=0
Z= I1 when S=1
Z S I 0 SI1

A 2:1 MUX.
I0

2:1
I1

MUX

Generalization of the TT:

S
0
1

Z
1
1

Z S 1 S 1 1

S Z
1 1
0 0

S Z
Z S 1 S 0
S

0 1
1 0

Z S 1 S 0

=S

S Z
Z S I 0 SI1 is the function

0 I0
1 I1

implemented by the above 2:1 MUX. Such a TT in general provides a

decomposition of the final function Z into constituent functions I0 & I1

Thus, the 2:1 MUX can also be implemented by logic gates:

I0

2:1 MUX : S
I1

I0
I1

2:1

A 2:1 MUX selects input Ii if S0 = I

[If S0 = 0, Z = I0
S0 = 1, Z = I1]

MUX

S0

I0
I1
I2
I3

4:1
MUX

The same can be said about

a 4:1 MUX:
Input Ii is selected (Z=Ii)
if S1S0 combination represents
the number i in binary.

S1 S0

In general, # of data inputs (Iis) is 2n

# of control I/Ps = n
[If S1S0 = 00 (#0), Z = Io
S1S0 = 01 (#1), Z = I1
S1S0 = 10 (#2), Z = I2
S1S0 = 11 (#3), Z = I3]
A generalized or symbolic TT

S1 S0

0
0
1
1

I0
I1
I2
I3

0
1
0
1

Z S1S 0 I 0 S1S 0 I1 S1S 0 I 2 S1S 0 I 3

I0
I1

2 :1
n

I 2n 1
Sn-1

S1 S0

In general for a 2n:1 MUX with control signals/inputs

Sn-1 S1S0 & data inputs I0, , I 2n,1
Z = Ii when Sn-1 S1S0 combination represents #i in binary.
8

Design of MUXes using Divide-&-Conquer

Saw the design of a 2:1 MUX using T-gates, as well as logic gates
Messy and expensive to design larger MUXes using a flat TT based approach
A 4:1 MUX can be hierarchically constructed using 2:1 MUXes
Idea: Divide the selection problem by bits of the select/control variables
These inputs should
have different lsb or S0 values,
since their sel. is based on S0.
All other bits should be equal.
Inputs selected are those w/
I0
the same lsb or S0 values. So
2:1
further selection needs to be
based on the non-lsb bits.
MUX

I1

S0
I2
I3
These inputs should
have different lsb or S0
values, since their sel. is
based on S0. All other
bits should be equal.

2:1
MUX

S0

2:1
MUX

S1
MSB

LSB of control variables

I0
I1
I2
I3

4:1
MUX

S0 S1
9

When S0=0, I0, I2 get selected at the 1st level, i.e., Input w/ 0
in LSB.
When S0=1, I1, I3 (LSB=1) get selected at the 1st level.
If S0 = 0, I0, I2, become the 0th & 1st inputs to the next level.
At the next level, the I/P order # is determined by the rest of the
bits of their index after stripping off the LSB.
Thus I0
I0
At level 2
I2
I1
0 0
1 0

(# 0)
(# 2)
strip away for the 2nd level inputs.
10

I0
I0
From level 1
I2
I1
S0=0
01

I1
I3

strip

Level 1
11

S0=1

Level 2

strip

I0
I1

2:1

MUX

S1

Z= I0 of level 2
(I0 of level 1), S1=0.
= I1 of level 2
(I2 of level1) if S1=1.
Z= I0 of Level 2
(I1 of Level1) if S1=0
= I1 of level 2
(I3 of level 1) if S1=1

Thus the design works as a 4:1 MUX.

11

An 8:1 MUX is designed similarly.

I0

I1
I2
I0
I1
I2
I3
I4
I5
I6
I7

8:1
MUX Z

I3

These inputs should

have different lsb or S0
values, since their sel. is
based on S0 (all other
remaining, i.e., unselected
bit values should be the
same). Similarly for other
i/p pairs at 2:1 Muxes at
this level.

2:1

I4

I0

MUX
S0

2:1

I2

MUX
S0

I5
S2 S1 S0

Selected when S0 = 0

2:1
MUX
S0

I6

2:1

I7

MUX

I1
I3
I5

4:1
MUX

I4

S2 S1
I6
I7

S0
Selected when S0 = 1
12

Opening up the 8:1 MUXs hierarchical design

Selected when S0 = 0

I0

I1
I0
I1
I2
I3
I4
I5
I6
I7

I2

8:1
MUX Z

I3

These inputs should

have different lsb or S0
values, since their sel. is
based on S0 (all other
remaining, i.e., unselected
bit values should be the
same). Similarly for other
i/p pairs at 2:1 Muxes at
this level.

MUX

I5

Selected when
S0 = 0, S1 = 1, S2=1

S0

2:1

I2

MUX
S0

I4
S2 S1 S0

2:1

I0

2:1
MUX

I4

2:1

I7

MUX

S0

I2

2:1
MUX

I6

2:1
MUX

I6

S2

S1

S0

I6

2:1
MUX
S1

I6

Selected when S0 = 0, S1 = 1.
These i/ps should differ in S2
These inputs should
have different S1 values,
since their sel. is based on
S1 (all other remaining, i.e.,
unselected bit values should
be the same). Similarly for
other i/p pairs at 2:1 Muxes
13
at this level.

8:1 MUXs: Input groupings for a different control variable order (S 2, S0, S1)
Selected when S2 = 1

Seed input

I0
+/- bit 2

I4
+/- bit 0

I0
I1
I2
I3
I4
I5
I6
I7

8:1
MUX Z

+/- bit 1

I5

These inputs should

have different lsb or S2
values, since their sel. is
based on S2 (all other
remaining, i.e., unselected
bit values should be the
same). Similarly for other
i/p pairs at 2:1 Muxes at
this level.

+/- bit 2

MUX

Selected when
S0 = 0, S1 = 1, S2=1

S2

2:1

I5

MUX
S2

+/- bit 1

S2 S1 S0

I1

2:1

I4

I2
2:1
+/- bit 2
MUX
I6

+/- bit 0

I3
I7

+/- bit 2

I6

MUX

S2

I4

2:1
MUX

I6

2:1
MUX

I6

S1

S0

S2

2:1

2:1
MUX
S0

I7

Selected when S2 = 1, S0 = 0.
These i/ps should differ in S1
These inputs should
have different S0 values,
since their sel. is based on
S0 (all other remaining, i.e.,
unselected bit values should
be the same). Similarly for
other i/p pairs at 2:1 Muxes
14
at this level.

General D&C/Hierarchical Design of a 2n :1 MUX

2:1

I0

S0

2n:1
MUX

2:1

S0

I 2n 1
Sn-1 S0

Design Strategy:

2
2:1
MUXes
n-1

2n-1 :1
MUX

2:1
S0

Sn-1 S1

First select inputs based on S0, using 2n-1 2:1 Muxes; 2n-1 inputs get selected on 2n-1
lines
The problem now reduces to that of a 2n-1:1 Mux
Continue recursively (to a 2n-2:1, 2n-3:1, ., 4:1, 2:1 Mux design problems) until the
final output is obtained.
Cost = 2n -1 2:1 Muxes = 6*(2n -1) gate inputs (6 is the gate-i/p cost of a 2:1 Mux)
Compare to flat design: Cost = (n+1)*2n (each 1st level AND gate has n select i/ps
and an Ij i/p for which the select i/p combination at the AND gate represents integer
j; there are 2n such AND gates) + 2n (2nd level OR gate i/ps) = (n+2)*2n gate inputs
(will actually require more for n > 4, as large gates required for a 2-level impl. are
not desirable (e.g., driving resistance become too large). More expensive for n > 4
(for 2-level design, if at all that is possible), and even more expensive for a multilevel design.
Note that both costs are exp. in n, but linear in the # m of inputs (m = 2 n), which is15
the important parameter.

Using MUXes to Realize Logic Circuits

Example:

f ( A, B, C ) m(0,2,6,7)

-- Use A,B,C as control inputs to an 8:1 MUX.

-- Treat the data inputs I0, , I7 as possible minterms of f:
Input Ii is a minterm if #i appears in the m notation of f.
If Ii is a minterm of f, it should be connected to a 1, otherwise
it should be connected to a 0.
1
0
1
0
0
0
1
1

I0
I1
I2
I3
I4
I5
I6
I7

8:1
MUX

S2 S1 S0
B

16

A 3-variable function can always be implemented by only an 8:1

MUX (i.e., no extra logic needed).
Interestingly, a 3-var. function can also always be implemented
by only a 4:1 MUX (assuming vars & their complements are
avail.).
Note: Can represent a function in terms of all combinations of
any subset of variables. E.g., any f (A,B,C) = AB(I0) + AB(I1) +
AB(I2) + AB (I3), where the Ijs can be 0, 1, C or C

It is a generalization of Shannons expansion theorem (which is for

two combinations of a single variable): f(X) = xi*f(X,xi=1) +
xi*f(X,xi=0)

Example f(A,B,C) = m(0,2,6,7)

Can determine Ijs using a K-Map: Select any 2 variables, say,
A,B, for the 2 control inputs
In a 3-var. K-map, group together squares into 2-squares in
which the other variable C varies, but A,B remains constant.
Form implicants only within 2-squares and write out the withinAB 00
01 as 11
10
2-squares
square sub-function
the min-cost
sum of a subset of these
C
implicants (choosing essential implicants first, etc., just like we
0
1
1 via K-maps
1
do for a full
function
or QM/QM+).

ABC

1
A BC

AB

17

 The function now is in terms of combinations of A, B ( A B , A B, etc.)

ANDed with either C, C , 1, or 0
Note: 0 is ANDed with an A,B combination (e.g., AB above) when the
2-square corresponding to that combination does not have any 1s,
i.e., when none of the product terms obtained from the K-map in the
above manner has that combination of A, B in them.

Connect either C, C , 1, 0 to the appropriate data input

corresponding to the A,B combination they are ANDed with in the
expression for f.
Thus f ( A B )C ( A B )C ( AB ) 0 ( AB) 1
Note again that a 4:1 MUX implements the function
f ( A B ) I 0 ( A B ) I1 ( AB ) I 2 ( AB ) I 3 ;

Thus for the above f, I 0 C , I1 C

I 2 0, and I 3 1

18

Corresponding generalized TT

C
C
0
1

0
1
2
3

4:1
MUX
S1 S0
A B

A B

0
0
1
1

C
C

0
1
0
1

0
1

-- A general n-variable function f(An-1, An-2, , A0)

Implementation possible using a 2n: 1 MUX (w/o requiring any
extra gates)? Yes.
Implementation possible using a 2n-1: 1 MUX (w/o requiring
any extra gates) ? Yes (assuming complemented variables are
available).
19

E.g.: A 4-var. function f(A,B,C,D)

Choose A, B, C as the control inputs
AB
CD 00
00

ABCD
01

10

01

1
1

11
10

11

AB C

A B CD

D
D

0
1
1
0
0
0

0
1
2
3
4
5
6
7

A BC

8:1
MUX

A B

f ( A B C ) D ( A B C ) D ( A BC ) 0 ( A BC ) 1
( AB C ) 1 ( AB C ) 0 ( ABC ) 0 ( ABC ) 0
20

-- In general, a 2i : 1 MUX, where i < n-1, can be used to implement

an n-var. function f(An-1, ,A0) by choosing any i variables, say,
Ai-1, , A0 ( This is just an example of i variables; you can choose
any i of the n variables) as the control inputs of the MUX. However,
for i < n-1, extra logic gates may be required.
-- Express f in terms of all combinations of Ai-1, , A0 (using
Shannons expansion recursively i times for each of these vars in
turn) as:
f ( Ai 1 Ai 2 A0 ) g 0 ( An 1 , , Ai ) ( Ai 1 Ai 2 A0 ) g1 ( An 1 , , Ai )
( Ai 1 Ai 2 A0 ) g 2i 1 ( An 1 , , Ai )

Where gk ( An 1, , Ai ) is a function of An-1,,Ai that in f ANDs with

the kth product-term/combination p(Ai-1..0k) of variables Ai-1, , A0
i
21
0

1
that represents the binary # k,
, i.e., in Shannons
terminology gk ( An 1, , Ai ) = p(Ai-1..0k) f(An-1, , Ai, p(Ai-1..0k) =1)

 Thus we get the implementation:

g0(An-1,, Ai+1)

I0

2i:1
MUX
g 2i 1 ( An 1 , , Ai 1 )

I 2i 1

Where each
gk may need
extra logic
gates for its
implementation.

Ai-1 A0

The trick is to choose the right i variables so that the total #

of logic gates needed for the gks is minimum (this is a hard
problem but interesting and beneficial to choose).

22

Heuristic Technique for gate-minimized design of a n-var. function using a 2 i:1 MUX:
PIs can only be formed within each groups of squares in which the control vars. are
constant (constant areas), which are 4-squares in the example below.
To min. # of gates, choose the i control vars such that the largest-size implicants & the
smallest # of them can be formed in its set const. areas.
Main idea of how to achieve this: Form all PIs in the full K-map, and choose the constant
areas that break as few of the EPIs (in red below) as possible, and then break as few of the
obvious choices (in blue below) of other PIs as possible, or if all of the rest of the non-EPI
choices are not obvious, then break as few as possible of each set of choices [each set
represents a set of alternate PIs, and breaking a set means breaking all PIs in the set].
Then, in each constant-area, form the SOP sub-expression for all the MTs in that area, just
like in a full K-Map (i.e., for all PIs in each area, determine and select all EPIs in that
area, cover remaining MTs in that area by the least-cost set of the remaining PIs).
Example : 4-var. function f(A,B,C,D) ; n=4. Let i=2
For i=2 (2 control variables from A,B,C,D for a 4:1 MUX), the K-map needs to be partitioned
into groups of 4-squares, such that within each 4-square the 2 control variables are constant.

AB
CD 00
00

01 11 10

01

11
10

1
1

AB
CD 00
00

01 11 10

01

EPIs 11
10

AC const. (green)
[1 break]

1
1

AB
CD 00
00 d 1
01

11
10

CD const. (orange)
[3 breaks]

d1

01 11 10

d1

b1

1
1 c d

BD const. (blue)
[2 breaks]

AB
CD 00
00
01
11
10

01 11 10

1c
a

1
1c 1

d
b

1
1

AD const. (maroon)
[2 breaks]
23

AB
CD 00
00

01

11

10

01 11 10

c1

1 b
1

00
ABD

01

11

10

01

10

4-squares where
A,B = constant
A,B are the
mux control vars.

1
1
1

11

BC const. (yellow)
[1 break]

AB C

AB
CD 00

AB const. (lt. green)

[0 breaks]

A BC

A study of the 1s in the above K-map tells us that this is achieved by the set of 4-squares
that are the columns of the K-map, i.e., for control variables A, B.
Then, in each constant-area, form the SOP sub-expression for all the MTs in that area, just
like in a full K-Map (i.e., for all PIs in each area, determine and select all EPIs in that
area, cover remaining MTs in that area by the least-cost set of the remaining PIs).
We thus obtain: f ( A B )( D ) ( A B )(C ) ( AB )(C ) ( AB )(0)
D

Implementation:
C
No logic gates needed!
C
(NOTE: This will not
always be the case)
0

0
1
2
3

4:1
MUX

S1 S0

24

A B

 If we choose A,C as the control variables (which has 1 break),

then the 4-squares w/ constant A, C are:
AB
CD 00
00

ABCD

01

01

10

11

10

1
1

11

A CD

AB C

1
A BC

Grouping 1s only within the 4-squares, we get 4 terms

A B C D , A CD , A BC , and AB C: all are essential (within their
constant areas)

25

-- We thus obtain f in terms of all combinations of A, C as

f A B C D A CD A BC AB C
( A C )( B D ) ( A C )( D B ) ( AC )( B ) ( AC )(0)

I0

I1

D
B

B
0

2
3

4:1
MUX

I2

I3
f

S1 S0
A C

-- Thus choosing A,C as control variables, results in 2 extra 2 i/p

gates (gate i/p cost = 4) compared to choosing A, B, for which the
cost = 0.
26