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5-<1>
Chapter 5 :: Topics
Introduction
Arithmetic Circuits
Number Systems
Sequential Building Blocks
Memory Arrays
Logic Arrays
5-<2>
Introduction
Digital building blocks:
Gates, multiplexers, decoders, registers, arithmetic circuits,
counters, memory arrays, logic arrays
5-<3>
1-Bit Adders
Half
Adder
Full
Adder
Cout
B
Cout
B
0
1
0
1
S
=
Cout =
Cout
Cin
A
0
0
1
1
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Cout
S =
Cout =
Copyright 2007 Elsevier
5-<4>
1-Bit Adders
Half
Adder
Full
Adder
Cout
B
Cout
B
0
1
0
1
S
=
Cout =
Cout
0
0
0
1
Cin
A
0
0
1
1
S
0
1
1
0
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Cout
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
S =
Cout =
Copyright 2007 Elsevier
5-<5>
1-Bit Adders
Half
Adder
Full
Adder
Cout
B
Cout
B
0
1
0
1
Cout
0
0
0
1
S
=AB
Cout = AB
Cin
A
0
0
1
1
S
0
1
1
0
Cin
0
0
0
0
1
1
1
1
A
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
Cout
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
S = A B Cin
Cout = AB + ACin + BCin
Copyright 2007 Elsevier
5-<6>
(slow)
(fast)
(faster)
Symbol
A
Cout
Cin
S
Copyright 2007 Elsevier
5-<7>
Ripple-Carry Adder
Chain 1-bit adders together
Carry ripples through entire chain
Disadvantage: slow
A31
Cout
B31
+
S31
A30
C30
B30
+
S30
C29
A1
C1
B1
+
S1
A0
C0
B0
Cin
+
S0
5-<8>
5-<9>
Carry-Lookahead Adder
Compute carry out (Cout) for k-bit blocks using generate and
propagate signals
Some definitions:
A column (bit i) produces a carry out by either generating a carry out
or propagating a carry in to the carry out.
Generate (Gi) and propagate (Pi) signals for each column:
A column will generate a carry out if Ai AND Bi are both 1.
Gi = Ai Bi
A column will propagate a carry in to the carry out if Ai OR Bi is 1.
Pi = Ai + Bi
The carry out of a column (Ci) is:
Copyright 2007 Elsevier
Carry-Lookahead Addition
Step 1: compute generate (G) and propagate (P) signals for
columns (single bits)
Step 2: compute G and P for k-bit blocks
Step 3: Cin propagates through each k-bit propagate/generate
block
5-<11>
Carry-Lookahead Adder
For example, we can calculate generate and propagate
signals for a 4-bit block (G3:0 and P3:0) :
A 4-bit block will generate a carry out if column 3 generates a carry
(G3) or if column 3 propagates a carry (P3) that was generated or
propagated in a previous column as described by the following
equation:
5-<12>
B27:24 A27:24
B7:4 A7:4
S27:24
B3
A3
S7:4
B2
A2
C2
B1
A1
C1
A0
C0
S3
S2
S1
S0
Cin
Cin
G3
P3
G2
P2
G1
P1
G0
P3:0
Cout
Cin
S3:0
B0
G3:0
B3:0 A3:0
P3
P2
P1
P0
5-<13>
tpg_block :
tAND_OR : delay from Cin to Cout of the final AND/OR gate in the k-bit
CLA block
5-<14>
Prefix Adder
Computes the carry in (Ci-1) for each of the columns as fast
as possible and then computes the sum:
Si = (Ai Bi) Ci
Computes G and P for 1-bit, then 2-bit blocks, then 4-bit
blocks, then 8-bit blocks, etc. until the carry in (generate
signal) is known for each column
Has log2N stages
5-<15>
Prefix Adder
A carry in is produced by being either generated in a
column or propagated from a previous column.
Define column -1 to hold Cin, so
G-1 = Cin, P-1 = 0
Prefix Adder
The generate and propagate signals for a block spanning bits
i:j are:
Gi:j = Gi:k Pi:k Gk-1:j
Pi:j = Pi:kPk-1:j
5-<17>
14
13
14:13
12
11
12:11
13:7
10:7
12:7
14
13
12
Legend
11
10
8:7
9:7
9:-1
8:-1
6:5
11:7
15
10:9
14:11 13:11
14:7
10
4:3
6:3
5:3
6:-1
5:-1
2:1
-1
0:-1
2:-1
4:-1
1:-1
3:-1
7:-1
i
i:j
Ai B i
Pi:i
Copyright 2007 Elsevier
Pi:k Pk-1:jGi:k
Gk-1:j
Gi-1:-1 Ai Bi
Gi:i
Pi:j
Gi:j
5-<18>
Si
5-<19>
5-<20>
tCLA
= 9.6 ns
= tpg + tpg_block + (N/k 1)tAND_OR + ktFA
= [100 + 600 + (7)200 + 4(300)] ps
tPA
= 3.3 ns
= tpg + log2N(tpg_prefix ) + tXOR
= [100 + log232(200) + 100] ps
= 1.2 ns
5-<21>
Subtracter
Symbol
Implementation
A
B
N
N
N
+
N
Y
5-<22>
Comparator: Equality
Symbol
Implementation
A3
B3
B
4
=
Equal
A2
B2
A1
B1
Equal
A0
B0
5-<23>
B
N
N
[N-1]
A<B
5-<24>
B
N
ALU
N
Y
3F
F2:0
Function
000
A& B
001
A| B
010
A+ B
011
not used
100
A & ~B
101
A | ~B
110
A- B
111
SLT
5-<25>
ALU Design
A
B
N
F2
Cout
+
[N-1] S
Zero
Extend
N
2
N
Y
Copyright 2007 Elsevier
F1:0
F2:0
Function
000
A& B
001
A| B
010
A+ B
011
not used
100
A & ~B
101
A | ~B
110
A- B
111
SLT
5-<26>
B
N
F2
Cout
+
[N-1] S
Zero
Extend
N
F1:0
Y
Copyright 2007 Elsevier
5-<27>
B
N
F2
Cout
Zero
Extend
2
N
Y
Copyright 2007 Elsevier
+
[N-1] S
F1:0
Shifters
Logical shifter: shifts value to left or right and fills empty spaces with
0s
Ex: 11001 >> 2 =
Ex: 11001 << 2 =
Rotator: rotates bits in a circle, such that bits shifted off one end are
shifted into the other end
Ex: 11001 ROR 2 =
Ex: 11001 ROL 2 =
5-<29>
Shifters
Logical shifter: shifts value to left or right and fills empty spaces with
0s
Ex: 11001 >> 2 = 00110
Ex: 11001 << 2 = 00100
Rotator: rotates bits in a circle, such that bits shifted off one end are
shifted into the other end
Ex: 11001 ROR 2 = 01110
Ex: 11001 ROL 2 = 00111
5-<30>
Shifter Design
A3 A2 A1 A0
shamt1:0
2
00
S1:0
01
Y3
10
11
00
shamt1:0
01
>>
Y2
10
A3:0
S1:0
11
Y3:0
00
01
S1:0
Y1
10
11
00
01
10
S1:0
Y0
11
5-<31>
5-<32>
Multipliers
Steps of multiplication for both decimal and binary
numbers:
Partial products are formed by multiplying a single digit of the
multiplier with the entire multiplicand
Shifted partial products are summed to form the result
Decimal
230
x 42
460
+ 920
9660
Binary
multiplicand
multiplier
partial
products
result
230 x 42 = 9660
Copyright 2007 Elsevier
0101
x 0111
0101
0101
0101
+ 0000
0100011
5 x 7 = 35
5-<33>
4 x 4 Multiplier
A3
A2
B0
B1
A B
4
A3 A2 A1 A0
x
B3 B2 B1 B0
A3B0 A2B0 A1B0 A0B0
A3B1 A2B1 A1B1 A0B1
A3B2 A2B2 A1B2 A0B2
x
8
+
P7
P1
P0
A1
A0
0
0
B2
0
B3
0
P7
P6
P5
P4
P3
P2
5-<34>
P1
P0
Division Algorithm
Q = A/B
R: remainder
D: difference
R=A
for i = N-1 to 0
D=R-B
if D < 0 then Qi = 0, R = R
else
Qi = 1, R = D
// R < B
// R B
R = 2R
Copyright 2007 Elsevier
5-<35>
4 x 4 Divider
5-<36>
Number Systems
What kind of numbers do you know how to represent using
binary representations?
Positive numbers
Unsigned binary
Negative numbers
Twos complement
Sign/magnitude numbers
5-<37>
5-<38>
Fixed-Point Numbers
Fixed-point representation of 6.75 using 4 integer bits and 4
fraction bits:
01101100
0110.1100
2
-1
-2
2 + 2 + 2 + 2 = 6.75
The binary point is not a part of the representation but is
implied.
The number of integer and fraction bits must be agreed upon
by those generating and those reading the number.
Copyright 2007 Elsevier
5-<39>
Fixed-Point Numbers
Ex: Represent 6.510 using an 8-bit binary representation with
4 integer bits and 4 fraction bits.
5-<40>
Fixed-Point Numbers
Ex: Represent 7.510 using an 8-bit binary representation with
4 integer bits and 4 fraction bits.
01111000
5-<41>
5-<42>
5-<43>
01111000
10000111
+
1
10001000
5-<44>
Floating-Point Numbers
The binary point floats to the right of the most significant 1.
Similar to decimal scientific notation.
For example, write 27310 in scientific notation:
273 = 2.73 102
5-<45>
Floating-Point Numbers
1 bit
8 bits
23 bits
Sign
Exponent
Mantissa
5-<46>
Floating-Point Representation 1
Convert the decimal number to binary:
22810 = 111001002 = 1.11001 27
1 bit
0
Sign
8 bits
00000111
Exponent
23 bits
11 1001 0000 0000 0000 0000
Mantissa
5-<47>
Floating-Point Representation 2
First bit of the mantissa is always 1:
22810 = 111001002 = 1.11001 27
1 bit
0
Sign
8 bits
00000111
Exponent
23 bits
110 0100 0000 0000 0000 0000
Fraction
5-<48>
Floating-Point Representation 3
Biased exponent: bias = 127 (011111112)
Biased exponent = bias + exponent
Exponent of 7 is stored as:
127 + 7 = 134 = 0x100001102
1 bit
0
Sign
8 bits
10000110
Biased
Exponent
23 bits
110 0100 0000 0000 0000 0000
Fraction
5-<49>
Floating-Point Example
Write the value -58.2510 using the IEEE 754 32-bit floatingpoint standard.
5-<50>
Floating-Point Example
Write the value -58.2510 using the IEEE 754 32-bit floatingpoint standard.
Convert the decimal number to binary:
58.2510 =
1 bit
8 bits
23 bits
Sign
Exponent
Fraction
In hexadecimal:
Copyright 2007 Elsevier
5-<51>
Floating-Point Example
Write the value -58.2510 using the IEEE 754 32-bit floatingpoint standard.
First, convert the decimal number to binary:
58.2510 = 111010.012 = 1.1101001 25
1 bit
8 bits
1 100 0010 0
Sign Exponent
23 bits
110 1001 0000 0000 0000 0000
Fraction
In hexadecimal: 0xC2690000
Copyright 2007 Elsevier
5-<52>
00000000
00000000000000000000000
11111111
00000000000000000000000
11111111
00000000000000000000000
NaN
11111111
non-zero
5-<53>
Double-Precision:
64-bit notation
1 sign bit, 11 exponent bits, 52 fraction bits
bias = 1023
5-<54>
Down
Up
Toward zero
To nearest
Down:
Up:
Toward zero:
To nearest:
1.100
1.101
1.100
1.101 (1.625 is closer to 1.578125 than 1.5 is)
5-<55>
Floating-Point Addition
1.
2.
3.
4.
5.
6.
7.
8.
5-<56>
5-<57>
8 bits
01111111
Exponent
23 bits
100 0000 0000 0000 0000 0000
Fraction
1 bit
8 bits
0
10000000
Sign Exponent
23 bits
101 0000 0000 0000 0000 0000
Fraction
5-<58>
5-<59>
8 bits
10000001
Exponent
23 bits
001 1000 0000 0000 0000 0000
Fraction
5-<60>
Counters
Increments on each clock edge.
Used to cycle through numbers. For example,
000, 001, 010, 011, 100, 101, 110, 111, 000, 001
Example uses:
Digital clock displays
Program counter: keeps track of current instruction executing
Symbol
Implementation
CLK
CLK
Q
Reset
Copyright 2007 Elsevier
N
r
Reset
5-<61>
Shift Register
Shift a new value in on each clock edge
Shift a value out on each clock edge
Serial-to-parallel converter: converts serial input (Sin) to
parallel output (Q0:N-1)
Implementation:
Symbol:
CLK
Q
Sin Sout
Sin
Sout
Q0
Q1
Q2
QN-1
5-<62>
D1
0
1
0
1
Q0
D2
DN-1
0
1
Q1
0
1
Q2
Sout
QN-1
5-<63>
An M-bit data value can be read or written at each unique Nbit address.
Address
Array
M
Copyright 2007 Elsevier
Data
5-<64>
Memory Arrays
Two-dimensional array of bit cells
Each bit cell stores one bit
An array with N address bits and M data bits:
Address
Array
Data
Copyright 2007 Elsevier
Address
Array
Data
11
0 1 0
10
1 0 0
01
1 1 0
00
0 1 1
depth
width
5-<65>
22 3-bit array
Number of words: 4
Word size: 3-bits
For example, the 3-bit word stored at address 10 is 100
Example:
Address
Address Data
2
Array
Data
11
0 1 0
10
1 0 0
01
1 1 0
00
0 1 1
depth
width
5-<66>
Memory Arrays
Address
10
1024-word x
32-bit
Array
32
Data
5-<67>
Example:
5-<68>
Example:
5-<69>
Memory Array
Wordline:
similar to an enable
allows a single row in the memory array to be read or written
corresponds to a unique address
only one wordline is HIGH at any given time
2:4
Decoder
11
Address
wordline3
10
01
00
bitline2
wordline2
wordline1
wordline0
bitline1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
Data2
Data1
bitline0
Data0
5-<70>
Types of Memory
Random access memory (RAM): volatile
Read only memory (ROM): nonvolatile
5-<71>
5-<72>
5-<73>
Types of RAM
Two main types of RAM:
Dynamic random access memory (DRAM)
Static random access memory (SRAM)
5-<74>
5-<75>
DRAM
Data bits stored on a capacitor
Called dynamic because the value needs to be refreshed
(rewritten) periodically and after being read:
Charge leakage from the capacitor degrades the value
Reading destroys the stored value
bitline
wordline
stored
bit
5-<76>
DRAM
bitline
wordline
stored + +
bit = 1
bitline
wordline
stored
bit = 0
5-<77>
SRAM
bitline
bitline
wordline
5-<78>
Memory Arrays
2:4
Decoder
11
Address
wordline3
10
01
00
bitline2
wordline2
wordline1
wordline0
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
Data2
bitline
bitline1
bitline0
Data1
Data0
bitline
wordline
5-<79>
5-<80>
5-<81>
ROM Storage
Address Data
11
0 1 0
10
1 0 0
01
1 1 0
00
0 1 1
depth
width
5-<82>
ROM Logic
Data2 = A1 A0
Data1 = A1 + A0
Data0 = A1A0
5-<83>
5-<84>
2:4
Decoder
11
A, B
10
01
00
X
5-<85>
10
01
00
bitline2
wordline3
wordline2
wordline1
wordline0
bitline1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
Data2
Data1
bitline0
Data0
Data2 = A1 A0
Data1 = A1 + A0
Copyright 2007 Elsevier
Data0 = A1A0
5-<86>
2:4
Decoder
11
A, B
wordline3
10
01
00
bitline2
wordline2
wordline1
wordline0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 1
stored
bit = 1
stored
bit = 0
stored
bit = 1
stored
bit = 0
stored
bit = 0
stored
bit = 0
stored
bit = 0
X
Copyright 2007 Elsevier
bitline1
bitline0
Z
5-<87>
Truth
Table
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
A1
A0
01
10
11
bitline
stored
bit = 0
stored
bit = 0
stored
bit = 0
stored
bit = 1
5-<88>
Multi-ported Memories
Port: address/data pair
3-ported memory
2 read ports (A1/RD1, A2/RD2)
1 write port (A3/WD3, WE3 enables writing)
A1
A2
A3
WE3
RD1
RD2
M
M
Array
WD3
5-<89>
[2:0] RAM[255:0];
assign rd = RAM[a];
always @(posedge clk)
if (we)
RAM[a] <= wd;
endmodule
5-<90>
Logic Arrays
Programmable logic arrays (PLAs)
AND array followed by OR array
Perform combinational logic only
Fixed internal connections
5-<91>
PLAs
X = ABC + ABC
Y = AB
Inputs
M
Implicants
AND
ARRAY
OR
ARRAY
Outputs
A
OR ARRAY
ABC
ABC
AB
AND ARRAY
5-<92>
AND
ARRAY
Implicants
OR
ARRAY
Outputs
OR ARRAY
ABC
ABC
AB
AND ARRAY
5-<93>
5-<94>
5-<95>
5-<96>
5-<97>
2 registered outputs:
XQ
YQ
2 combinational outputs:
X
Y
5-<98>
5-<99>
(A)
(B)
(C)
(X)
F3
0
0
0
0
1
1
1
1
F2
0
0
1
1
0
0
1
1
F1
0
1
0
1
0
1
0
1
F
0
1
0
0
0
0
1
0
(A)
(B)
(Y)
G4 G3 G2 G1
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
G
0
0
1
0
0
0
A
B
G4
G3
G2
G1
0
A
B
C
F4
F3
F2
F1
5-<100>
5-<101>