CSC 3650 Introduction to Computer Architecture

Spring 2011

Time: 3:30 to 6:30

Meeting Days: W

Location: Oxendine 1237B

Textbook: Essentials of Computer Architecture, Author: Douglas E. Comer, 2005, Pearson Prentice Hall

Chapter Four
The Variety of Processors and
Computational Engines

Dr. Chuck Lillie

State Tables
State tables describe the activities of a state diagram.

State Diagrams for Alarm Clock

Example
(a)

Moore Machine
Arrows are transitions
Labels on arrows are inputs
Outputs are associated with
states
1 indicates that turn off
alarm is yes
0 indicates that turn off
alarm is no
(b) Mealy Machine
Outputs associated with
transitions
Labels on directed arrows
indicates input/output

State Tables for JK Flip-Flop

Flip-flop has two states, Y and Z, and two inputs J and K
For given present state Y, and an input 0,0, the next state is Y and
the output is 0
For present state Z, and inupt 0,0, the next state is Z and the
output is 1

State Tables for JK Flip-Flop

Reduced version of previous state table
Dont care conditions
When in Y, it doesnt matter the value of K, the next state is
always Y with output of 0 for J = 0, and Z, 1 for J = 1
When in Z, it doesnt matter the value of J, the next state and
output are determined by K

State Diagrams for J-K FlipFlop

If you are in state Y and J = 0 and K = X (dont care) will go

back to state Y and output 0.
If in state Y and J = 1 and K = X (dont care), will go to state Z
and output 1.
If in state Z and K = 0 and J = X, go back to state Z and output 1.
If in state Z and K = 1 and J = X will go to state Y and output 0.
This is a Moore Machine model because the output is part of the
states not the transitions.

JK Flip-Flop with Modified

Outputs

(b) State Diagram

(a) State Table
In this example, the output is 1 if the state changes and 0 if the
machine remains in the same state. This is best modeled with a
Mealy machine, because the output occurs with the transition. For
this to be modeled with a Moore machine additional states would
have to be present to represent this system.

Modulo 6 Counter
Counts from 0 to 5 and starts over

U is input, 0 is
indicates no change,
1 is increment
counter
C used to indicate
when counter goes
from 101 to 000
Values 110 and 111
not used

(a) State Diagram for Modulo 6

Counter Modeled as Mealy
Machine

(b) State Diagram for Modulo 6

Counter Modeled as Moore
Machine

State Table for String Checker

A string checker inputs a

string of bits, one bit per
clock cycle. When the
previous three bits form the
pattern 110, it sets output
M = 1; otherwise M = 0.
The system checks bits 1,
2, 3 then 2, 3, 4 then 3, 4,
5. Etc.

State Diagrams for String

Checker

Mealy

Moore

State Table for String Checker with

Revised State Assignments.

Only 4 states needed

Practical Perspective: Mealy and

Moore State Diagrams for Revised
String Checker

States for the Tool Booth Controller

R: light is red
G: light is green
A: Alarm sounded

State Table for Toll Booth Controller

State Diagram for Moore

Machine for Toll Booth
Controller

(a) State Diagram for Mealy

Machine for the Modulo 6
Counter

Use 3 bits to identify the state because there are six states
Identifies state based on output (state 100 is reached when output is 0100

(b) State Diagram for the Moore

Machine for the Modulo 6
Counter

(a) Generic Mealy Machine

Register used to store current state value

Inputs used to set the output and select the next state

(b) Mealy Machine for Modulo 6

Counter

Since we chose our state names to correspond to the output values,

the logic for both is the same so we can use the same logic circuit.

(a) Generic Moore Machine

(b) Moore Machine

Implementation of Modulo 6
Counter

State Table for Modulo 6 Counter

Karnaugh Maps (K-maps) for the

Next State of Modulo 6 Counter

N2 = P2P0 + P2U + P1P0U

N1 = P1P0 + P1U + P2P1P0U

N0 = P0U + P0U

Next State Logic for Modulo 6

Counter

Two State Tables for the Modulo 6

Counter Divided by Input U

K-Maps for Modulo 6 Counter for Multiplexer

U=0
P2/P1P0
0
1

00
0
1

01
0
1

11
0
X

U=1
10
0
X

N2 = P 2
P2/P1P0
0
1

N0 = P 0

00
0
1

01
0
0

11
1
X

10
0
X

11
0
X

10
1
X

N2 = P 2 P 0 + P 1 P 0
00
0
0

01
0
0

11
1
X

10
1
X

N1 = P 1

P2/P1P0
0
1

P2/P1P0
0
1

P2/P1P0
0
1

00
0
0

01
1
0

N1 = P1P0 + P2P1P0

00
0
0

01
1
1

11
1
X

10
0
X

P2/P1P0
0
1
N0 = P 0

00
1
1

01
0
0

11
0
X

10
1
X

Preliminary Implementation of the Next State

Logic for the Modulo 6 Counter Using a
Multiplexer

Final Implementation of the Next State

Logic for Modulo 6 Counter Using
Multiplexer
U = 0, this input is selected

U = 1, this input is selected

Modulo 6 Counter Implemented with a Look-Up

ROM
P2 P1 P0 U

Output for Modulo 6 Counter

K-maps for Output of Modulo 6 Counter Mealy Machine

Mealy Machine
P2P1/P0U
00
01
11
10

00
0
0
X
1

Moore Machine
01
0
0
X
1

11
0
1
X
0

10
0
0
X
1

V2 = P2P0 + P2U + P1P0U

P2P1/P0U
00
01
11
10

00
0
1
X
0

01
0
1
X
0

11
1
0
X
0

10
0
1
X
0

V1 = P1P0 + P1U + P2P1P0U

P2P1/P0U
00
01
11
10

00
0
0
X
0

01
1
1
X
1

11
0
0
X
0

10
1
1
X
1

11
0
0
X
1

10
0
0
X
0

V0 = P0U + P0U
P2P1/P0U
00
01
11
10

00
1
0
X
0

01
0
0
X
0

C = P2P1P0U + P2P0U

P2/P1P0 00 01 11 10
0
0 0 0 0
1
1 1 X X
V2 = P 2
P2/P1P0 00 01 11 10
0
0 0 1 1
1
0 0 X X
V1 = P 1

P2/P1P0 00 01 11 10
0
0 1 1 0
1
0 1 X X
V0 = P 0
P2/P1P0 00 01 11 10
0
1 0 0 0
1
0 0 X X
C = P2P1P0

Mealy Machine Implementation of Modulo 6

Counter

Moore Machine Implementation of Modulo 6

Counter

(a) Moore Machine Implementation

of Modulo 6 Counter Using Lookup
ROM

(b)ROM Data for Moore Machine Implementation of Modulo 6

Counter

P2 P1 P0 U

N2 N1 N0 C

(a) Alternative Design using Counter

and Decoder to Implement Modulo 6
Counter

(b) Moore Machine Implementation of

Modulo 6 Counter Using Counter and
Decoder

State Table for String Checker

K-Maps for Next
State and Output

Next State Values

Output
P2P1/P0I
00
01
11
10
N2 = P 1

00
0
1
1
0

01
0
1
1
0

11
0
1
1
0

10
0
1
1
0

P2P1/P0I
00
01
11
10
N1 = P o

00
0
0
0
0

01
0
0
0
0

11
1
1
1
1

10
1
1
1
1

P2P1/P0I
00
01
11
10
N0 = I

00
0
0
0
0

01
1
1
1
1

11
1
1
1
1

10
0
0
0
0

P2P1/P0U 00
00
0
01
0
11
1
10
0
M = P 2 P1 P0

01
0
0
1
0

11
0
0
0
0

10
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0

Moore Machine Implementation of Eight-State String

Checker

(a) Moore Modulo 6 Counter Including Unused States

(b) Invalid Design for Modulo 6 Counter with Unused

States

Dummy States for Unused State Values

State Table for Modulo 6 Counter with

Unused States

K-Maps for Modulo 6 Counter with Unused States

Output

Next State

P2P1/P0U
00
01
11
10
V2 = P 2

00
0
0
1
1

01
0
0
1
1

11
0
0
1
1

10
0
0
1
1

P2P1/P0U 00 01 11 10
00
0 0 0 0
01
0 0 1 0
11
0 0 0 0
10
1 1 0 1
N2 = P2P1P0 + P2P1U + P2P1P0U

P2P1/P0U
00
01
11
10
V1 = P1

00
0
1
1
0

01
0
1
1
0

11
0
1
1
0

10
0
1
1
0

P2P1/P0U 00 01 11 10
00
0 0 1 0
01
1 1 0 1
11
0 0 0 0
10
0 0 0 0
N1 = P2P1P0 + P2P1U + P2P1P0U

P2P1/P0U
00
01
11
10

00
0
0
1
0

01
0
0
1
0

11
1
1
1
1

10
1
1
1
1

01
1
0
0
0

11
0
0
0
0

10
0
0
0
0

V0 = P 0 + P 2 P1
P2P1/P0U 00
00
1
01
0
11
0
10
0
C = P2P1P0

P2P1/P0U 00 01 11 10
00
0 1 0 1
01
0 1 0 1
11
0 0 0 0
10
0 1 0 1
N0 = P2P0U + P2P0U + P1P0U + P1P0U

Generic Asynchronous Moore

Machine

State Values and State Diagram

for Asynchronous Modulo 6
Counter

State Table for Modulo 6 Counter with

Revised State Values

K-Maps for Modulo 6 Counter Asynchronous Design

Output

Next State

P2P1/P0U
00
01
11
10
V2 = P 2 P0

00
0
X
1
1

01
0
X
1
1

11
0
0
0
X

10
0
0
0
X

P2P1/P0U
00
01
11
10
V1 = P 1 P0

00
0
X
0
0

01
0
X
0
0

11
0
1
1
X

10
0
1
1
X

P2P1/P0U
00
01
11
10

00
0
X
0
1

01
0
X
0
1

11
1
0
1
X

10
1
0
1
X

P2P1/P0U
00
01
11
10

00
0
X
1
1

01
0
X
1
0

11
0
1
1
X

10
0
0
1
X

P2P1/P0U 00 01
00
0 0
01
X X
11
1 0
10
0 0
N1 = P1U + P0U

11
1
1
1
X

10
0
1
1
X

P2P1/P0U 00 01
00
0 1
01
X X
11
0 0
10
0 0
N0 = P2U + P0U

11
1
1
0
X

10
1
1
1
X

N2 = P2U + P1U

V0 = P2P1 + P2P0 + P1P0

P2P1/P0U 00
00
1
01
X
11
0
10
0
C = P2P1P0

01
1
X
0
0

11
0
0
0
X

10
0
0
0
X

Hardware Implementation of Modulo

6 Counter Asynchronous Design

Revised State Diagram for

Modulo 6 Counter

Converting a Mealy State Diagram to

a Moore State Diagram

FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.

FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.

FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.

FromEssentialsofComputerArchitecturebyDouglasE.Comer.ISBN0131491792.2005PearsonEducation,Inc.Allrightsreserved.