CS2100 Computer Organisation

More building blocks

BUILDING BLOCKS

Introduction
Decoders
Encoders
Priority Encoders
Demultiplexers
Multiplexers
Carry Select Adders

Shifters

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INTRODUCTION

Four common and useful circuit blocking blockss:

Decoder
Demultiplexer
Encoder
Multiplexer

Block-level outlines of MSI circuits:

code

input

decoder

mux

select
AY11/12 Sem 1

entity

data

entity

encoder

data

demux

code

output

select
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DECODERS

DECODERS (1/5)

Codes are frequently used to represent entities, eg: your

name is a code to denote yourself (an entity!).

These codes can be identified (or decoded) using a decoder.

Given a code, identify the entity.

Convert binary information from n input lines to (maximum of)

2n output lines.

Known as n-to-m-line decoder, or simply n:m or nm decoder

(m 2n).

May be used to generate 2n minterms of n input variables.

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DECODERS (2/5)

Example: If codes 00, 01, 10, 11 are used to identify four light
bulbs, we may use a 2-bit decoder.
2x4
F0
X Dec F

2-bit
code

Bulb 0
Bulb 1
Bulb 2
Bulb 3

F2
F3

This is a 24 decoder which selects an output line based on

the 2-bit code supplied.
Truth table:
X Y F F F F

0
0
1
1
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0
1
0
1

1
0
0
0

0
1
0
0

0
0
1
0

0
0
0
1

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DECODERS (3/5)

From truth table, circuit for 24

decoder is:

F0 = X'Y'

Note: Each output is a 2variable minterm (X'Y',

X'Y, XY' or XY)
X
0
0
1
1

Y F0
0 1
1 0
0 0
1 0

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F1 F2 F3
0 0 0
1 0 0
0 1 0
0 0 1

F1 = X'Y
F2 = XY'
F3 = XY

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DECODERS (4/5)

F0 = x'y'z'

Design a 38 decoder.

F1 = x'y'z
F2 = x'yz'
x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z F0
0 1
1 0
0 0
1 0
0 0
1 0
0 0
1 0

F1
0
1
0
0
0
0
0
0

F2
0
0
1
0
0
0
0
0

F3
0
0
0
1
0
0
0
0

F4
0
0
0
0
1
0
0
0

F5
0
0
0
0
0
1
0
0

F6
0
0
0
0
0
0
1
0

F7
0
0
0
0
0
0
0
1

F3 = x'yz
F4 = xy'z'
F5 = xy'z
F6 = xyz'
F7 = xyz

x
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z
8

DECODERS (5/5)

In general, for an n-bit code, a decoder could select

up to 2n lines:

n-bit
code

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n to 2n
decoder

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up to 2n
output lines

DECODERS: IMPLEMENTING FUNCTIONS

(1/5)

A Boolean function, in sum-of-minterms form decoder to

generate the minterms, and an OR gate to form the sum.

Any combinational circuit with n inputs and m outputs can be

implemented with an n:2n decoder with m OR gates.

Good when circuit has many outputs, and each function is

expressed with few minterms.

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10

DECODERS: IMPLEMENTING FUNCTIONS

(2/5)

Example: Full adder

S(x, y, z) = m(1,2,4,7)
C(x, y, z) = m(3,5,6,7)

3x8
Dec
x

S2

S1

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S0

0
1
2
3
4
5
6
7

x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

C S
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1

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11

DECODERS: IMPLEMENTING FUNCTIONS

(3/5)

3x8
Dec

0 x

S2

0 y

S1

0 z

S0

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0
1
2
3
4
5
6
7

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x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

C S
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1

12

DECODERS: IMPLEMENTING FUNCTIONS

(4/5)

3x8
Dec

0 x

S2

0 y

S1

1 z

S0

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0
1
2
3
4
5
6
7

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x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

C S
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1

13

DECODERS: IMPLEMENTING FUNCTIONS

(5/5)

3x8
Dec

1 x

S2

1 y

S1

1 z

S0

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0
1
2
3
4
5
6
7

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x
0
0
0
0
1
1
1
1

y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1

C S
0 0
0 1
0 1
1 0
0 1
1 0
1 0
1 1

14

DECODERS WITH ENABLE (1/2)

Decoders often come with an enable control signal, so that

the device is only activated when the enable, E = 1.

Truth table:
E X
1 0
1 0
1 1
1 1
0 X

Y
0
1
0
1
X

F0 = EX'Y'

F0 F1 F2 F3
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
0 0 0 0

F1 = EX'Y
F2 = EXY'
F3 = EXY

Circuit of a 24 decoder
with enable:
X

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E
15

DECODERS WITH ENABLE (2/2)

In the previous slide, the decoder has a one-enable control

signal, i.e. the decoder is enabled with E=1.

In most MSI decoders, enable signal is zero-enable, usually

denoted by E' or . The decoder is enabled when the signal is
zero (low).
E X
1 0
1 0
1 1
1 1
0 X

Y
0
1
0
1
X

F0 F1 F2 F3
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
0 0 0 0

Decoder with 1-enable

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E'
0
0
0
0
1

X
0
0
1
1
X

Y
0
1
0
1
X

F0 F1 F2 F3
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
0 0 0 0

Decoder with 0-enable

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16

LARGER DECODERS (1/4)

Larger decoders can be

constructed from smaller
ones.

Example: A 38 decoder
can be built from two 24
decoders (with oneenable) and an inverter.

w
x
y

w
x
y

S2
S1
S0

3x8
Dec

S1
S0

S1
S0

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2x4
Dec
E

2x4
Dec
E

F0 = w'x' y'
F1 = w' x' y
:
:
F 7 = w x y

0
1
:
:
7

0
1
2
3

F0 = w' x' y'

F1 = w' x' y
F2 = w' x y'
F3 = w' x y

0
1
2
3

F4 = w x' y'
F5 = w x' y
F6 = w x y'
F7 = w x y
17

LARGER DECODERS (2/4)

w
x
y

w
x
y

S1
S0

S1
S0

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2x4
Dec
E

2x4
Dec
E

0
1
2
3

S2
S1
S0

3x8
Dec

0
1
:
:
7

F0 = w'x' y'
F1 = w' x' y
:
:
F 7 = w x y

F0 = w' x' y'

F1 = w' x' y
F2 = w' x y'
F3 = w' x y

F4 = w x' y'
F5 = w x' y
F6 = w x y'
F7 = w x y

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18

LARGER DECODERS (3/4)

Construct a 416 decoder

from two 38 decoders
with one-enable.
w
x
y
z

w
x
y
z

S3
S2
S1
S0

4x16
Dec

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0
1
:
:
15

F0
F1
:
:
F15

S2
S1
S0

S2
S1
S0

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3x8
Dec

3x8
Dec

0
1
:
7

F0
F1
:
F7

0
1
:
7

F8
F9
:
F15

19

LARGER DECODERS (4/4)

Note: The input, w and its complement, w', are used to select
either one of the two smaller decoders.

Decoders may also have zero-enable and/or negated outputs.

Normal outputs = active high
Negated outputs = active low

Exercise: What modifications should be made to provide an

ENABLE input for the 38 decoder and the 416 decoder
created in the previous two slides?

Exercise: How to construct a 416 decoder using five 24

decoders with enable?

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20

STANDARD MSI DECODER (1/2)

74138 (3-to-8 decoder)

74138 decoder module.

(a) Logic circuit.
(b) Package pin configuration.
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21

STANDARD MSI DECODER (2/2)

74138 decoder module.

(c) Function table.

(c)

74138 decoder module.

(d) Generic symbol.
(e) IEEE standard logic symbol.
Source:The Data Book Volume 2, Texas
Instruments Inc.,1985

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22

DECODERS: IMPLEMENTING FUNCTIONS

REVISIT (1/2)

Example: Implement the following function using a 38

decoder and appropriate logic gate
f(Q,X,P) = m(0,1,4,6,7) = M(2,3,5)

We may implement the function in several ways:

Using a decoder with active-high outputs with an OR gate:
f(Q,X,P) = m0 + m1 + m4 + m6 + m7
Using a decoder with active-low outputs with a NAND gate:
f(Q,X,P) = (m0' m1' m4' m6' m7' )'
Using a decoder with active-high outputs with a NOR gate:
f(Q,X,P) = (m2 + m3 + m5 )' [ = M2 M3 M5 ]
Using a decoder with active-low outputs with an AND gate:
f(Q,X,P) = m2' m3' m5'

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23

DECODERS: IMPLEMENTING FUNCTIONS

REVISIT (2/2)
3x8
Dec
Q
X
P

A
B
C

0
1
2
3
4
5
6
7

f(Q,X,P)
= m(0,1,4,6,7)
f(Q,X,P)

(a) Active-high decoder with OR gate.

3x8
Dec
Q
X
P

A
B
C

0
1
2
3
4
5
6
7

A
B
C

0
1
2
3
4
5
6
7

f(Q,X,P)

(b) Active-low decoder with NAND gate.

3x8
Dec

f(Q,X,P)
Q
X
P

(c) Active-high decoder with NOR gate.

AY11/12 Sem 1

Q
X
P

3x8
Dec

A
B
C

0
1
2
3
4
5
6
7

f(Q,X,P)

(d) Active-low decoder with AND gate.

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24

READING ASSIGNMENT

Reducing Decoders
Read up DLD pg 134 138.

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25

ENCODERS

ENCODERS (1/4)

Encoding is the converse of decoding.

Given a set of input lines, of which exactly one is high, the
encoder provides a code that corresponds to that input line.
Contains 2n (or fewer) input lines and n output lines.
Implemented with OR gates.
Example:
F0

Select via
switches

AY11/12 Sem 1

F1
F2
F3

D0

4-to-2
Encoder

D1

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2-bits
code

27

ENCODERS (2/4)

Truth table:

With K-map, we obtain:

D0 = F1 + F3
D1 = F2 + F3

Circuit:

AY11/12 Sem 1

F0 F1
1 0
0 1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
1 0
1 0
1 0
1 1
1 1
1 1
1 1

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F2 F3
0 0
0 0
1 0
0 1
0 0
1 1
0 1
1 0
1 1
0 1
1 0
1 1
0 0
0 1
1 0
1 1

D1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X

D0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
28

ENCODERS (3/4)

Example: Octal-to-binary encoder.

At any one time, only one input line has a value of 1.
Otherwise, we need priority encoder (to be discussed in
tutorial).
Inputs

D0
1
0
0
0
0
0
0
0
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D1
0
1
0
0
0
0
0
0

D2
0
0
1
0
0
0
0
0

D3
0
0
0
1
0
0
0
0

D4
0
0
0
0
1
0
0
0

Outputs

D5
0
0
0
0
0
1
0
0

D6
0
0
0
0
0
0
1
0

D7
0
0
0
0
0
0
0
1

x
0
0
0
0
1
1
1
1

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y
0
0
1
1
0
0
1
1

z
0
1
0
1
0
1
0
1
29

ENCODERS (4/4)

Example: Octal-to-binary encoder.

D0
D1

x = D4 + D5 + D6 + D7

D2
D3

y = D2 + D3 + D6 + D7

D4
D5
D6
D7

z = D1 + D3 + D5 + D7

An 8-to-3 encoder

Exercise: Can you design a 2n-to-n encoder without using Kmap?

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30

PRIORITY ENCODER (1/3)

An important variant of the standard encoder

Used in a lot of I/O devices

Aim: break ties

What if one or more of the inputs goes high?

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31

PRIORITY ENCODER (2/3)

Each of the inputs is assigned a priority.

The most significant bit of the input has the

highest priority while the least significant bit has
the lowest priority.

Tie breaker: if two input lines goes high, only the

higher priority one will be considered.

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32

PRIORITY ENCODER (3/3)

F0 F1
1 0
0 1
0 0
0 0
0 0
Standard 0
0
encoder
0 1
0 1
0 1
1 0
1 0
1 0
1 1
1 1
1 1
1 1
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F2 F3
0 0
0 0
1 0
0 1
0 0
1 1
0 1
1 0
1 1
0 1
1 0
1 1
0 0
0 1
1 0
1 1

D1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X

D0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X

F3 F2
1 X
0 1
0 0
0 0

F1
X
X
1
0

F0
X
X
X
X

D1
1
1
0
0

D0
1
0
1
0

Priority encoder

(Implementation a tutorial
exercise.)

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33

DEMULTIPLEXERS

DEMULTIPLEXERS (1/2)
Given an input line and a set of selection lines, a
demultiplexer directs data from the input to one selected
output line.
Example: 1-to-4 demultiplexer.

Outputs
Y0 = DS1'S0'
Data D

demux

Y1 = DS1'S0
Y2 = DS1S0'
Y3 = DS1S0

S1 So
0 0
0 1
1 0
1 1

Y0
D
0
0
0

Y1
0
D
0
0

Y2
0
0
D
0

Y3
0
0
0
D

S1 S0
select
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35

DEMULTIPLEXERS (2/2)

It turns out that the demultiplexer circuit is actually identical to

a decoder with enable.

S1
S0

0
24
Decoder
1
A
B
2

Y0 = ?

Y3 = ?

Y1 = ?
Y2 = ?

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36

MULTIPLEXERS

MULTIPLEXERS (1/5)

A multiplexer is a device which has

A number of input lines
A number of selection lines
One output line

It steers one of 2n inputs to a single output line, using n

selection lines. Also known as a data selector.

inputs

2n:1
Multiplexer

output

...

select
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38

MULTIPLEXERS (2/5)

Truth table for a 4-to-1 multiplexer:

I0
d0
d0
d0
d0

I1
d1
d1
d1
d1

I2
d2
d2
d2
d2

I3
d3
d3
d3
d3

S1
0
0
1
1

S0
0
1
0
1

Inputs
I0
I1
I2
I3

Y
d0
d1
d2
d3

S1
0
0
1
1

Y
I0
I1
I2
I3

Inputs
0
4:1
1 MUX
Y
2
3
S1 S 0

Output

I0
I1
I2
I3

4:1
mux

S1 S 0
select

select
AY11/12 Sem 1

S0
0
1
0
1

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39

MULTIPLEXERS (3/5)

Output of multiplexer is
sum of the (product of data lines and selection lines)

Example: Output of a 4-to-1 multiplexer is:

Y=?

A 2n-to-1-line multiplexer, or simply 2n:1 MUX, is made from an

n:2n decoder by adding to it 2n input lines, one to each AND
gate.
S S
Y
1

0
0
1
1

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0
1
0
1

I0
I1
I2
I3

40

MULTIPLEXERS (4/5)

A 4:1 multiplexer circuit:

I0

I0

I1

I1
Y

I2

I2
I3

I3
0 1 2 3
2-to-4
Decoder

S1

S1 S0
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S0

41

MULTIPLEXERS (5/5)

An application:

Helps share a single communication line among a number of

devices.
At any time, only one source and one destination can use the
communication line.

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42

MULTIPLEXER IC PACKAGE

Some IC packages have a few multiplexers in each package

(chip). The selection and enable inputs are common to all
multiplexers within the package.
A0

Y0

A1

Y1

A2

Y2

A3

Y3
E S Output Y
1 X
all 0s
0 0 select A
0 1 select B

B0
B1
B2
S

B3

(select)

Quadruple 2:1 multiplexer

E'
(enable)
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43

LARGER MULTIPLEXERS (1/4)

Larger multiplexers can be constructed from smaller ones.
An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (note placement of selector lines):

I0
I1
I2
I3

4:1
MUX
S1 S0

I4
I5
I6
I7

4:1
MUX

2:1
MUX

S2

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Y
I0
I1
I2
I3
I4
I5
I6
I7

S1 S0
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44

LARGER MULTIPLEXERS (2/4)

I0 I1 I2

I0
I1
I2
I3

4:1
MUX
2:1
MUX

S1 S0
I4
I5
I6
I7

4:1
MUX

I0 I1 I6

I4 I5 I6
S2

S1 S0

When S2S1S0 = 000

When S2S1S0 = 001

When S2S1S0 = 110

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S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Y
I0
I1
I2
I3
I4
I5
I6
I7

45

LARGER MULTIPLEXERS (3/4)

Another implementation of an 8-to-1 multiplexer

using smaller multiplexers: When
I0

2:1
MUX

I1
I2
I3

I2

2:1
MUX

I0

S0
4:1
MUX

S0
I4
I5

2:1 I4
MUX
S0 I6
I7

I0

S2
0
0
0
0
1
1
1
1

S1
0
0
1
1
0
0
1
1

S0
0
1
0
1
0
1
0
1

Y
I0
I1
I2
I3
I4
I5
I6
I7

S2 S 1
2:1
MUX
S0

AY11/12 Sem 1

S2S1S0 = 000

I6

Q: Can we use only 2:1 multiplexers?

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LARGER MULTIPLEXERS (4/4)

A 16-to-1 multiplexer can

be constructed from five 4to-1 multiplexers:

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STANDARD MSI MULTIPLEXER (1/2)

(b)

74151A 8-to-1 multiplexer. (a) Package configuration. (b) Function table.

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STANDARD MSI MULTIPLEXER (2/2)

(c)

74151A 8-to-1 multiplexer. (c) Logic diagram. (d) Generic logic symbol.
(e) IEEE standard logic symbol.
Source: The TTL Data Book Volume 2. Texas Instruments Inc.,1985.
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MULTIPLEXERS: IMPLEMENTING
FUNCTIONS (1/3)

Boolean functions can be implemented using multiplexers.

A 2n-to-1 multiplexer can implement a Boolean function of n

input variables, as follows:
1. Express in sum-of-minterms form. Example:
F(A,B,C) = A'B'C + A'BC + AB'C + ABC'
= m(1,3,5,6)
2. Connect n variables to the n selection lines.
3. Put a 1 on a data line if it is a minterm of the function, or 0
otherwise.

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MULTIPLEXERS: IMPLEMENTING
FUNCTIONS (2/3)

F(A,B,C) = m(1,3,5,6)
0
1
0
1
0
1
1
0

0
1
2
3 mux
4
5
6
7

A B C

This method works because:

F

Output = m0I0 + m1I1 + m2I2 + m3I3

+ m4I4 + m5I5 + m6I6 + m7I7

Supplying 1 to I1,I3,I5,I6 , and 0 to the

rest:
Output = m1 + m3 + m5 + m6

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MULTIPLEXERS: IMPLEMENTING
FUNCTIONS (3/3)

Example: Use a 74151A to implement

f(x1,x2,x3) = m(0,2,3,5)

Realization of f(x1,x2,x3) = m(0,2,3,5).

(a) Truth table.
(b) Implementation with 74151A.
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USING SMALLER MULTIPLEXERS (1/6)

Earlier, we saw how a 2n-to-1 multiplexer can be used to

implement a Boolean function of n (input) variables.

However, we can use a single smaller 2(n-1)-to-1 multiplexer to

implement a Boolean function of n (input) variables.

Example: The function

F(A,B,C) = m(1,3,5,6)
can be implemented using a 4-to-1 multiplexer (rather than an
8-to-1 multiplexer).

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USING SMALLER MULTIPLEXERS (2/6)

Lets look at this example:

F(A,B,C) = m(0,1,3,6) = A'B'C' + A'B'C + A'BC + ABC'
1
1
0
1
0
0
1
0

0
1
2
3 mux
4
5
6
7

1
C
0
C'

A B C

0
1
2

mux

A B

Note: Two of the variables, A and B, are applied as selection

lines of the multiplexer, while the inputs of the multiplexer
contain 1, C, 0 and C'.

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USING SMALLER MULTIPLEXERS (3/6)

Procedure
1. Express Boolean function in sum-of-minterms form.
Example: F(A,B,C) = m(0,1,3,6)

2. Reserve one variable (in our example, we take the least

significant one) for input lines of multiplexer, and use the
rest for selection lines.
Example: C is for input lines; A and B for selection lines.

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USING SMALLER MULTIPLEXERS (4/6)

3. Draw the truth table for function, by grouping inputs by
selection line values, then determine multiplexer inputs by
comparing input line (C) and function (F) for corresponding
selection line values.

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MUX
input

?
?
?
?

0
1
2

mux

A B

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USING SMALLER MULTIPLEXERS (5/6)

Alternative: What if we use A for input lines, and B, C for

selector lines?
A

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
0
1
0
0
1
0

?
?
?
?

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A
0
0
0
0
1
1
1
1

Mux
Input
1
C
0
C

0
1
2

mux

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F
1
1
0
1
0
0
1
0

A' (when BC = 00)

B C

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USING SMALLER MULTIPLEXERS (6/6)

Example: Implement the function below with 74151A:

f(x1,x2,x3,x4) = m(0,1,2,3,4,9,13,14,15)

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CARRY-SELECT ADDERS (1/3)

Another way to add!

By the clever use of multiplexers

Recall the issue in addition:

The carry chain
But carry can only be 0 or 1!

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CARRY-SELECT ADDERS (2/3)

Goal: Add two n-bit numbers A and B to produce the result C
Trick: Split A, B and C into two equal halves: AH, AL, BH, BL and CH, CL
AH
cout

BH
cin

AH

AL

BH
cout

cout

cin

BL
+

cin

CL
2-to-1 MUX
MUX

cout
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CH
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CARRY-SELECT ADDERS (3/3)

Upper and lower half equal

About the same time to complete

Timing overhead is in the multiplexing

Needs more resources
But can do divide-and-conquer

Till we get small lengths that can be implemented

using simpler adders

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SHIFTERS

SHIFTERS

The left and right shift is a common operation

Left shift by 1 bit = multiply by 2

Right shift by 1 bit = divide by 2

0010 = 2

True of twos complement negative numbers?

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SHIFTERS

The left and right shift is a common operation

Left shift by 1 bit = multiply by 2

Right shift by 1 bit = divide by 2

0010 = 4
0100
2

True of twos complement negative numbers?

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SHIFTERS

The left and right shift is a common operation

Left shift by 1 bit = multiply by 2

0010 = 4
0100
2

Right shift by 1 bit = divide by 2

0101 = 5

True of twos complement negative numbers?

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SHIFTERS

The left and right shift is a common operation

Left shift by 1 bit = multiply by 2

0010 = 4
0100
2

Right shift by 1 bit = divide by 2

0101 = 2
0010
5

True of twos complement negative numbers?

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SHIFTERS

The left and right shift is a common operation

Left shift by 1 bit = multiply by 2

Right shift by 1 bit = divide by 2

True of twos complement negative numbers?
1110 = -2

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SHIFTERS

To get it right arithmetic shift

In arithmetic left shift, zero is used to fill in the

LSB

In arithmetic right shift, the original MSB is

duplicated at MSB and MSB-1 position

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SHIFTERS

The left and right shift is a common operation

Left shift by 1 bit = multiply by 2

Right shift by 1 bit = divide by 2

True of twos complement negative numbers?
0111 = 3

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SHIFTERS

LSB

MSB

7 6 5 4 3 2 1 0

LSB

MSB

LSB

7 6 5 4 3 2 1 0

LSB

7 6 5 4 3 2 1 0

MSB

MSB

Left shifts

7 6 5 4 3 2 1 0

0
Logical left shift

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0
Arithmetic left shift

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SHIFTERS

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

Right shifts

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

0100 = 4
7 6 5 4 3 2 1 0

0
Logical right shift

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Arithmetic right shift

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SHIFTERS

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

Right shifts

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

0010 = 2
7 6 5 4 3 2 1 0

0
Logical right shift

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SHIFTERS

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

Right shifts

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

1110 = -2
7 6 5 4 3 2 1 0

0
Logical right shift

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SHIFTERS

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

Right shifts

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

1111 = -1
7 6 5 4 3 2 1 0

0
Logical right shift

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But what
if I right
shift some
more???

Arithmetic right shift

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BARREL SHIFTERS

Barrel shifters perform fast shifting

In O(log n) steps

The key observation: given a shift amount x,

represent x as a binary string, xn-1x1x0
Now if xj = 1, then shift by 2j
Example: shift amount is 7, i.e. 01112, we can
perform the shift in 3 stages

Stage 0: shift by 4
Stage 1: shift by 2
Stage 2: shift by 1
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BARREL SHIFTERS
Use MUX!
X7

X6

X5

X4

X3

X2

S2

Shift by 2 stage

S1

0
Shift by 1 stage

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X0

Shift by 4 stage
0

X1

S0

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BARREL SHIFTERS
An Example:
X7

X6

X5

X4

X3

X2

S2 = 0

Shift by 2 stage

S1 = 1

0
Shift by 1 stage

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X0

Shift by 4 stage
0

X1

S0 = 1

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BARREL SHIFTERS
An Example:
X7

X6

X5

X4

X3

X2

S2 = 0

Shift by 2 stage

S1 = 1

0
Shift by 1 stage

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X0

Shift by 4 stage
0

X1

S0 = 1

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BARREL SHIFTERS
An Example:
X7

X6

X5

X4

X3

X2

S2 = 0

Shift by 2 stage

S1 = 1

0
Shift by 1 stage

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X0

Shift by 4 stage
0

X1

S0 = 1

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BARREL SHIFTERS
An Example:
X7

X6

X5

X4

X3

X2

S2 = 0

Shift by 2 stage

S1 = 1

0
Shift by 1 stage

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X0

Shift by 4 stage
0

X1

S0 = 1

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BARREL SHIFTERS
An Example:
X7

X6

X5

X4

X3

X2

X1

X0

Shift by 4 stage
0

S2 = 0

Shift by 2 stage

S1 = 1

0
Shift by 1 stage

S0 = 1
0

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X7

X6

X5

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X4

X3

81

BARREL SHIFTERS
An Example:
X7

X6

X5

X4

X3

X2

X1

X0

tic
e
thm
i
r
ta
u
bo
a
at
h
W

Shift by 2 stage
0
Shift by 1 stage
0

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t)
gSh2 = 0

Shift by 4 stage

X7

X6

X5

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X4

ri
(
t
if
sh

S1 = 1

S0 = 1

X3

82

END

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