8.

Central Processing Unit

The three types of CPU organization

1. Single AC
ADD X
AC AC + M[X]
Basic Computer
2. General Register
ADD R1, R2, R3 R1 R2 + R3
ADD R1, R2
R1 R1 + R2
IBM, VAX, SUN, CRAY
3. Stack
PUSH X
Stack[top] M[X]
ADD
Stack[top] Stack[top] + Stack[top-1]
Burrough 6600, 6700

R1 R2 + R3
Field:
SELA SELB SELD OPR
Symbol: R2 R3
R1 ADD
Control
Word:
010 011 001 00010

SELA SELB SELD Operation

R1
R2
R4
R5
R1
R2

R2 + R3 : 010
R2 - R3 : 010
R4 R5 : 100
R5 + R6 : 101
R2
: 010
R1 + R3 : 001

011
011
101
110
000
011

001
010
100
101
001
010

00010
00101
01000
00010
00000
00010

The Stack
LIFO(Last-In First-Out) List
1) Stand-alone stack
2) Memory stack

 1
The push operation
If FULL = 0
SP SP + 1
M[SP] DR
If (SP = 0 ) then (FULL 1)
EMTY 0
Else Stack-Overflow

The pop operation

Stand-alone stack

If EMTY = 0
DR M[SP]
SP SP - 1
If (SP = 0 ) then (EMTY 1)
FULL 0
Else Stack-Underflow

 1
The push operation

3000 ULR

If SP LLR
SP SP + 1
M[SP] DR
If (SP = LLR) then (FULL 1)
EMTY 0
Else Stack-Overflow

Upper-Limit Register

The pop operation

4001 LLR
Lower-Limit Register

Memory stack

If SP ULR
DR M[SP]
SP SP - 1
If (SP < ULR) then (EMTY 1)
FULL 0
Else Stack-Underflow

Reverse Polish Notation

1) Infix notation:
A+B
2) Prefix or Polish notation:
+ AB
3) Postfix or reverse Polish notation: AB +
1) Infix notation:
A*B+C*D
2) Prefix or Polish notation:
+*AB*CD
3) Postfix or reverse Polish notation: AB*CD*+
1) Infix notation:
(A+B)*(C*(D+E)+F)
2) Postfix or reverse Polish notation: AB+DE+C*F+*

34*56*+

The three types of CPU organization

1. Single AC
ADD X : AC AC + M[X]
2. General Register
ADD R1, R2, R3 : R1 R2 + R3
ADD R1, R2 :
R1 R1 + R2
3. Stack
PUSH X : M[SP] M[X]
ADD :
M[SP-1] M[SP] + M[SP-1]

Three-Address Instructions for X = (A+B)*(C+D)

ADD R1, A, B
ADD R2, C, D
MUL X, R1, R2
Two-Address Instructions for X = (A+B)*(C+D)
MOV
ADD
MOV
ADD
MUL
MOV

R1, A : R1 M[A]
R1, B : R1 R1 + M[B]
R2, C
R2, D
R1, R2
X, R1

One-Address Instructions for X = (A+B)*(C+D)

LOAD A
ADD
B
STORE T
LOAD C
ADD
D
MUL T
STORE X

Zero-Address Instructions for X = (A+B)*(C+D)

AB+CD+*
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X

RISC Instructions for X = (A+B)*(C+D)

LOAD R1, A
LOAD R2, B
LOAD R3, C
LOAD R4, D
ADD
R1, R1, R2
ADD
R3, R3, R4
MUL
R1, R1, R3
STORE X, R1

Memory operation

Register operation
Memory operation

 1
The purpose of Addressing Modes
1) Programming versatility( )
pointers to memory, counters for loop control,
indexing of data, program relocation
2) Reduction of the number of bits
in the addressing field

Addressing Modes
Implied Mode

CMA, ADD

Immediate Mode

R1 2

Register Mode

R1 R1 + 2

Register Indirect Mode R2 M[R1]

Autoincrement Mode

R1 R1 + M[R2], R2 R2 + 1

Autodecrement Mode R2 R2 - 1, R1 R1 + M[R2]

Addressing Modes

BR

Direct Address Mode

R1 M[AD]

Indirect Address Mode

R1 M[M[AD]]

(PC-)Relative
Address Mode

R1 M[AD+PC]

Indexed Addressing Mode

R1 M[AD+XR]

Base Register Addressing Mode R1 M[AD+BR]

AD
XR

 1
Computer Instructions
1. Data transfer
2. Data manipulation
3. Program control

LD @PTR
LD $DIF
LD #395

ADD with Carry for Double-Precision Addition

(Table 6-15)
LDA AL
ADD BL
STA CL
CLA
CIL
ADDC AH
ADD BH
C
STA CH
HLT
AH
AL
AL,
BL
+ BH
AH,
-------------BL,
CH
CL
BH,
CL,
CH,

SUB with Borrow for Double-Precision Subtraction

LDA AL
SUB BL
STA CL
CLA
LDA AH
SUBB BH
STA CH
HLT
AL,
AH,
BL,
BH,
CL,
CH,

B
-

AH
AL
BH
BL
-------------CH
CL

SUB

A = 101x1100
B = 00010000

If A B = 0, x = 0
If A B 0, x = 1

Conditional Branch Instructions

c8c7c6c5c4 c3 c2 c1 c0

111000000
A: 11110000
B + 1 : +1 1 1 0 1 1 0 0
-----------------------A-B: 11011100
C(c8) = 1

S(F7) = 1

B:

V(c8c7) = 0

00010100

Z=0

1) Unsigned numbers
A = 240, B = 20, A-B = 220
A-B = A+(2n B), C = 1 and Z = 0 A > B
2) Signed numbers
A = -16, B = 20, A-B = -36
S = 1, V = 0, Z = 0 A < B

Two unsigned numbers A and B

Two signed numbers A and B

Program Interrupt
The state of the CPU should be saved
1. The content of the program counter: PC(Subroutine Call
)
2. The content of all processor registers: AC, E
3. The content of certain status conditions: S, V, C, Z
PSW(Program Status Word)
Types of Interrupt
1. Hardware interrupts
External : power, I/O device
Internal : Stack-overflow, divide-by-zero
2. Software interrupts : OS call(Read, Write)

CISC Characteristics
1.
2.
3.
4.
5.
6.

Large number of instructions: 100~250

Some infrequently used instructions
A large variety of addressing modes: 5~20
Variable-length instruction formats: Figure 2.23
Instructions that manipulate operands in memory
Microprogrammed control unit

ADD R1, X: R1 R1 + M[X]

Computer Architecture
A Quantitative Approach

John L. Hennessy and

David A. Patterson,
2003(3rd),
Morgan Kaufman

RISC Characteristics
1.
2.
3.
4.
5.
6.
7.
8.
9.

Relatively few instructions

Relatively few addressing modes
Memory access limited to load and store instructions
All operations done within the registers of the CPU
Fixed-length, easily decoded instruction format
Single-cycle instruction execution
Hardwired rather than microprogrammed control
A relatively large number of processor registers
Use of overlapped register windows
to speed-up procedure call and return
10. Efficient instruction pipeline
11. Complier support for efficient translation
of high-level language programs
into machine language programs

 1
overlapped register windows

Overlapped Register Windows

# global registers: G = 10
# local registers in each window: L = 10
# registers common to two windows: C =
6
# windows: W = 4
# registers for each window
Window size = L + 2C + G (= 32)
The total number of registers
in the processor
Register file = (L + C)W + G (= 74)
Fig. 8-9: G = 10, L = 10, C = 6, and W = 4

Berkeley RISC I
ADD R22, R21, R23 : R23 R22 + R21
ADD R22, #150, R23 : R23 R22 + 150
ADD R0, R21, R22 : R22 R21 (Move)
ADD R0, #150, R22 : R22 150 (Load immediate)
ADD R22, #1, R22 : R22 R22 + 1

RISC and CISC examples