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Electronics Technology
Landon Johnson
Shift Registers
GATES
FLIP FLOPS
ENCODERS
DECODERS
SHIFT
REGISTERS
MULTIPLEXERS
DEMULTIPLEXERS
ADDERS
MEMORY
SMALL
MICROPROCESSORS
Lab 18.
CP QN
R
S
J
Q
CP
K QN
R
CP QN
R
S
J
Q
CP
K QN
R
CP QN
R
Lab 18.
data
in
clear
clk
S
J
Q
CP
K QN
R
S
J
Q
CP
K QN
R
S
J
Q
CP
K QN
R
S
J
Q
CP
K QN
R
Lab 27.
Q3
Q2
Q1
Q0
C
B
A
OVERVIEW OF
SHIFT REGISTERS
A shift register is a sequential logic device
made up of flip-flops that allows parallel or
serial loading and serial or parallel outputs
as well as shifting bit by bit.
Common tasks of shift registers:
Serial/parallel data conversion
UART (an example)
Time delay
Ring counter
Twisted-ring counter or Johnson counter
Memory device
CHARACTERISTICS OF
SHIFT REGISTERS
Number of bits (4-bit, 8-bit, etc.)
Loading
Serial
Parallel (asynchronous or synchronous)
Common modes of operation.
Parallel load
Shift right-serial load
Shift left-serial load
Hold
Clear
Recirculating or non-recirculating
SERIAL/PARALLEL DATA
CONVERSION
Shift registers can be used to convert from serialto-parallel or the reverse from parallel-to-serial.
Parallel out
Parallel out
Serial in
0 11 00 11 11 11 11
11
0
1 0 1 0 1 1 1 1
Parallel in
Serial out
Serial out
1
0
0
1
1
0
1
0
Data =
=0
1
Data
Inputs here:
Clock input:
(1) Data Clock Pulse 2
3
4
6
7
Positive-edge
Clock Pulse 1
5
8
(2) Clock
Clear
input:
triggering
(3) Clear
Active Clear
=0 =1
0
Deactivated = 1
4-bit
serial-in
parallel out
shift right
shift register
TEST
QUESTION #7
#2
#3
#4
#6
#5
QUESTION #1
What is the 4-bit output (bit A on left, D on right) after pulse 6?
1?
2?
3?
5?
4?
This is a ___ type shift register.
A. Serial-in, parallel out
A: Serial-in,
A: parallel-out
0100
1000
1100
0000
A:
0010
1001
B. Parallel-in, serial-out
Data
Data =
=1
1
00
Data
Data
=
Clock
ClockPulse
Pulse
Pulse2
4
Clock
Clock
Pulse
6
5
13
Clear
Clear =
=1
1
Clear
Clear
=
01
Parallel data
inputs
(Active LOW)
Recirculating
lines:
Pass
data
Note
thefrom
FFD to FFA
recirculating
on
each
lines.
clock pulse.
RECIRCULATING
SHIFT REGISTER
11
0
00
10
1
Parallel
Paralleldata
datainputs=
inputs=
only
only
C&
allD
D
Binactive
activated
activated
active
Clock
pulse8 7
1
2
3
5
6
Clockpulse
4
Clear
input=1 0
1
Clearinput=
Clear input
Serial data Right
inputLOW
active
used during
Serial Load Right
mode ofdata
operation
Parallel
inputs
Order: A, B, C, D
Serial
Leftloading
input
during data
Parallel
used during
Serial Load Left
mode of operation
Clock input
Mode
Controls:
L-to-H
triggering
Hold
Parallel load
Shift right
Shift left
74194 Universal 4-bit Shift Register IC.
Modes of operation: Hold, Parallel load, Shift right & Shift left.
An active LOW Clear (CLR) input overrides all others.
X = Irrelevant
TEST
QUESTION
QUESTION#3
#1
#2
#5
#6
#7
QUESTION #4- What is the mode of operation during and the output of the
The
What
What
74194
is
isthe
the
IC
mode
mode
couldof
of
be
operation
operation
described
during
during
as a 4-bit
and
andthe
(shift
theoutput
output
right,of
of
universal)
the
the
shift register after pulse 3?
shift
shiftregister
register.
registerafter
afterpulse
pulse2?
1?
4?
5?
6?
A:right,
Universal
A:A:
A:
Parallel
A:
A:
Shift
Shift
Clear,
Hold,
left,
load,
0000
0
1
001
1
0
010
0
1
101
00
? ? ? ?
0
CLR = 1
X
Serial R = 0
Parallel Load=
Load=
Parallel
01
10
00
0
0
Serial L = X
1
1
2
4
Clock pulse 6
3
5
(L-to-H)
(L-to-H)
1
S0= 0
0
S1= 1