Escolar Documentos
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Cultura Documentos
Power Estimation
Lecture 25
Alessandra Nardi
Interconnects
Signal Integrity
P/G integrity
Substrate coupling
Crosstalk
Parasitic Extraction
Reduced Order Modeling
Manufacturability
Power Estimation
Outline
Design for Manufacturability
Yield
Parametric Yield
Defect-related yield
Statistical Design
Power Estimation
Power consumption mechanisms
Different level of abstraction
Static or dynamic analysis
Parametric Yield
Process variations
Statistical Design
Need to account for process variations during
design phase
Statistical design
Nominal design
Yield optimization
Design centering
Statistical Design
Defect-related Yield
Manufacturing process may introduce some defects in the layout
Defect-related Yield
Defect-layout relationship
Yield in terms of area and design rules
Larger area lower yield
Smaller geometries higher sensitivity to defects
trade-off: yield loss must be expressed in terms of
the defect size and layout characteristics rather
than in terms of area alone
Defect-related Yield
Critical area
Model relationship between defect characteristics
(density and size distribution) and the probability of
the defect
The critical area, for a defect radius R, is defined as
the area on the layout where, if the center of a defect
is deposited a fault occurs:
Y exp{ Acr ( R)}
From 2D to 3D
optimization problem
From D. Singh et al Power Conscious CAD Tools
and Methodologies: A Perspective, IEEE Proc. 1995.
50%
20%
10%
Behavioral
RTL
Gate
Switch
Power
Analysis
RTL
Synthesis
Power
Analysis
Logic
Optimization
Power
Analysis
Transistor
Optimization
Power
Analysis
Dynamic Consumption
Due to load capacitance
Largest component
Vdd
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Digital Integrated Circuits2nd
Vdd
Vin
2
Edyn C L VDD
Vout
CL
Power=Energy/transition:
2
Pdyn C L VDD
f
n N
lim
N N
P av g = 0 1 C Vdd 2 f clk
L
Ideally zero
Vin
Not zero since rise and
fall time (tr and tf) are not zero
Power=Energy/transition:
2
CL
0.15
) f
IVDD (mA)
tr t f
Vout
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
VDD
In
Out
CL
ISC
Short-Circuit Currents
Psc I peak VDD (
tr t f
2
) f clk 01
Static Dissipation
Pstat I leakVDD
Complete
Completepower
powermodel
modelprovides
providesinfrastructure
infrastructurefor
foranalysis
analysisand
andoptimization
optimization
1997 Jan M. Rabaey
Power Estimation
Dynamic Analysis
Simulation
requires representative simulation vectors
Derived by designer
Automatic (Monte Carlo)
Power Estimation
Static Analysis
Propagation of switching probabilities
No input vectors needed
Much faster than simulation
Less accurate than simulation
Hard to model real delays
Glitches?
Power Estimation
Static Analysis Probability Propagation
AND gate
sp(1) = sp1 * sp2
tp(01) = sp * (1 - sp)
Propagate
1/2
1/4
1/2
7/16
1/2
Example
1/2
sp = 0.5 * 0.5 = 0.25
tp = 0.25 * (1 - 0.25) = 0.1875
1/4
1997 Jan M. Rabaey
Power Estimation
Static Analysis Probability Propagation
Power Estimation
Static Analysis Probability Propagation: Problems
Problem: Reconvergent
Fan-out:
Creates spatial
correlation between
signals
0.5
0.5
0.75
0.375?
0.5!
P(X) = P(B=1).(P(X=1 | B = 1)
Becomescomplexanduntractablerealfast
1997 Jan M. Rabaey
Power Optimization
Supply voltage reduction
Summary
Design for Manufacturability
Yield
Parametric Yield
Defect-related yield
Statistical Design
Power Estimation
Power consumptionmechanisms
Different level of abstraction
Static or dynamic analysis
Class Review
Fundamentals of Circuit Simulation
Overview
Equivalence Checking
FastMOS simulation
Timing Analysis
Hardware Description Languages
System C
Interconnects
Signal Integrity
Parasitic Extraction
Reduced Order Modeling
Manufacturability
Power Estimation