Designing with FPGA

Resources

Objectives
After completing this module, you will be able to:
Describe the I/O features of the Virtex-6 and Spartan-6 FPGAs
Describe block RAM and FIFO resources
Describe the available DSP48 resources
List other resources available in Virtex-6 and Spartan-6 FPGAs

Designing with FPGA Resources - 2

Copyright 2010 Xilinx

Lessons

I/O
Block RAMs and FIFO
DSP48 Resources
Other Features
Summary

Designing with FPGA Resources - 3

Copyright 2010 Xilinx

I/O Block Diagram

Logical Resources

Electrical Resources

IOLOGIC

IOSERDES

LVDS
Termination

Slave
IODELAY

IOLOGIC

IOSERDES

Designing with FPGA Resources - 4

IODELAY

Interconnect to FPGA fabric

Master

Copyright 2010 Xilinx

SelectIO Interface Versatility

Each pin can be input and (3-stateable) output
Each pin can be individually configured for
Internal termination, drive strength, input threshold, and weak pull-up or pull-down

Each I/O can have the same performance

Up to 1 Gbps single-ended and 1.4 Gbps differential

Each I/O supports 40 plus voltage and protocol standards, including

LVCMOS (2.5 V, 1.8 V,
1.5 V, and 1.2 V)
LVDS, bus LVDS, extended LVDS
LVPECL
Hyper Transport (LDT)

Designing with FPGA Resources - 5

HSTL (1.8 V, 1.5 V, Classes I, II, III, IV)

SSTL (2.5 V, 1.8 V, 1.5 V Classes I, II)

HSTL_I_12 (unidirectional only)

DIFF_SSTL_I

DIFF_HSTL_I_18,
DIFF_HSTL_I_18_DCI
DIFF_HSTL_I, DIFF_HSTL_I_DCI

DIFF_SSTL2_I_DCI

HSTL_II_T_DCI

DIFF_SSTL18_I,
DIFF_SSTL18_I_DCI
SSTL15

DIFF_HSTL_II_T_DCI

SSTL15_T_DCI

RSDS_25 (point-to-point)

DIFF_SSTL15_T_DCI

Copyright 2010 Xilinx

Virtex-6 FPGA Internal Termination Using DCI

Configures output driver impedance (series termination)
Provides input impedance match to
Vcco (single termination) or
Vcco (split termination, Thevenin equivalent)

Two reference pins per bank: VRP and VRN

Make DCI independent of voltage, temperature, and process variations
Connected to reference resistors (50 to 100 ohm)

DCI cascading feature

One banks VRP and VRN can also be shared by adjacent banks

Dynamically 3-stateable input termination (*_T_DCI)

Input termination is only enabled when the output driver is 3-stated
Vcco

VTT(50% of Vcco)

100
50

Equivalent
External HSTL_I
Termination
Designing with FPGA Resources - 6

100
Virtex-6 HSTL_I_DCI
Termination

Traditional FPGA
Copyright 2010 Xilinx

Virtex-6 Input and Output DDR

IDDR supports OPPOSITE_EDGE
(legacy mode), SAME_EDGE, and
SAME_EDGE_PIPELINED
ODDR is similar, but only supports
OPPOSITE_EDGE and SAME_EDGE
OLOGIC contains ODDR for both data
and 3-state enable

D
SR
OCE
CLK

D
R
CE

D
R
CE

D
R
CE

D
R
CE

OCE
Q1_A Q2_A Q1_B Q2_B Q1_C Q2_C Q1_D Q2_D Q1_E Q2_E Q1_F

Q1

Q1_A

Q1_B

Q1_C

Q1_D

Q2

Q2_A

Q2_B

Q2_C

Q2_D

Designing with FPGA Resources - 7

Q2

IDDR

CLK
D

Q1

Copyright 2010 Xilinx

Spartan-6 FPGA Input and Output DDR

Same-edge and opposite edge capability
Attribute: DDR_ALIGNMENT =
NONE (default), C0, or C1
DDR_ALIGNMENT = NONE

DDR_ALIGNMENT = C0 or C1

Designing with FPGA Resources - 8

Copyright 2010 Xilinx

I/O SERDES Capability

Parallel/Serial to Serial/Parallel Conversion

Includes input and output SERDES

OSERDES parallel-to-serial converter for both OQ
and TQ
ISERDES and OSERDES have independent CLK
and CLKDIV inputs

Arranged as master and slave IOB pair

IOB pairs share the same name with
P and N suffixes for master and slave
IOB pairs allow for differential I/O
Master ISERDES & OSERDES can use slave
resources to widen the interface

IOB side can be SDR or DDR

Designing with FPGA Resources - 9

Copyright 2010 Xilinx

MASTER
OSERDES

IOB

ISERDES

Master/Slave IOB Pair

SLAVE
OSERDES
ISERDES

IOB

Programmable Data Delay

Change the clock/data phase relationship for data capture
Adjust timing on a per-pin basis to accommodate board/package skew
Dynamically controllable
From Pad
From OLOGIC or
OSERDES

IDATAIN
ODATAIN

IODELAY

Delay Chain
INC/DEC

Delay
Delaygenerated
generatedininincrements
increments
Virtex-6:
Virtex-6:Delay
Delaysteps
stepsare
arecalibrated
calibrated
based
basedon
onREFCLK
REFCLKfrequency
frequency
Delay
Delaycan
canbe
bedynamically
dynamicallycontrolled
controlled

User
Interface

Virtex-6 only
REFCLK
Designing with FPGA Resources - 10

IDELAYCTRL
Copyright 2010 Xilinx

DATAOUT To Pad, ILOGIC,

ISERDES or
FPGA fabric

From FPGA
fabric

Use Examples
SDR resources utilizing ILOGIC and OLOGIC resources can be inferred
IDDR can be inferred
See Xilinx Answer Record 15776

ODDR, ISERDES, OSERDES, IDELAY, IODELAY, and IDELAYCTRL

resources must be instantiated
Instantiate primitives
Memory Interface Generator (MIG)

Designing with FPGA Resources - 11

Copyright 2010 Xilinx

Memory Interface Generator

Generates a complete memory
controller and interface design
Output: RTL, UCF,
documentation, and timing
analysis
VHDL or Verilog

Choose from a predefined

catalog of available devices
and interfaces
Checks SSO and all pin
selection rules

Included with the CORE

Generator software
Designing with FPGA Resources - 12

Copyright 2010 Xilinx

Apply Your Knowledge

1) Describe the I/O features of the Virtex-6 and Spartan-6 FPGAs

Designing with FPGA Resources - 13

Copyright 2010 Xilinx

Lessons

I/O
Block RAMs and FIFO
DSP48 Resources
Other Features
Summary

Designing with FPGA Resources - 14

Copyright 2010 Xilinx

Virtex-6 FPGA Block RAM and FIFO

36-kb size
One 36-kb block RAM or FIFO
Two independent 18-kb RAMs
One 18-kb RAM and one 18-kb FIFO

Performance up to 600 MHz

Multiple configurations
True dual port, simple dual port, single port

64kb x 1 integrated cascade logic

Maximum data width = 72
Byte-write enable
Integrated 64-bit error correction
Designing with FPGA Resources - 15

Copyright 2010 Xilinx

or
Dual-Port
BRAM

FIFO

Spartan-6 FPGA Block RAM

18-kb size
One 18-kb block RAM
9 Kb
block RAM

Two independent 9-kb RAMs

18 Kb
block
RAM

Performance up to 300 MHz

Multiple configurations
True dual port, simple dual port, single port

Maximum data width = 72

Byte-write enable

Designing with FPGA Resources - 16

Copyright 2010 Xilinx

or
9 Kb
block RAM

Block RAM Modes

1. Single-port block RAM: One read/write port

36-kb configurations

16k x 2, 8k x 4, 4k x 9, 2k x 18, 1k x 36, 512 x 72

Addr A

18-kb configurations

16k x 1, 8k x 2, 4k x 4, 2k x 9, 1k x 18, 512 x 36

Spartan-6: 256 x 72

Port A

36
Wdata A

36

Rdata A

9-kb configurations

8k x 1, 4k x 2, 2k x 4, 1k x 9, 512 x 18, 256 x 36

2. Simple dual-port block RAM: one read port, one write

port

Separate clock and address per port

Virtex-6 FPGA 36-kb and Spartan-6 FPGA 18-kb:

configurations up to 72 bits wide

Virtex-6 FPGA 18-kb and Spartan-6 FPGA 9-kb:

configurations up to 36 bits wide

Designing with FPGA Resources - 17

Copyright 2010 Xilinx

Addr B

36
Wdata B

Port B
Rdata B

36

Block RAM Modes

Continued

3. True dual-port block RAM

Separate clock and address per port

Can perform read and write operations

simultaneously and independently on
Port A and Port B

Addr A

Port A

36
Wdata A

Write operation also performs read

operation at same address

Mode can be read-before-write,

write-before-read, or no-change

Virtex-6 FPGA 36-kb and Spartan-6 FPGA 18-kb:

configurations up to 36 bits wide

Virtex-6 FPGA 18-kb and Spartan-6 FPGA 9-kb:

configurations up to 18 bits wide

Ports can be different widths

Designing with FPGA Resources - 18

Copyright 2010 Xilinx

36

Rdata A

36-kb
Memory
Array
Addr B

36
Wdata B

Port B
Rdata B

36

Block RAM Features

DQ
DQ

Virtex-6 FPGA: Built-in cascade logic for 64kb x 1

Cascade two adjacent 32-kb block RAMs without using
external CLB logic or compromising performance
Cascade option for larger arrays using external
CLB logic

Byte enables for configurations > 9 bits

Optional pipeline register for reads
Virtex-6 FPGA: Error Correcting Code (ECC)
Available on 512x72 simple dual-port RAM
or FIFO
No byte enables
64 bits of data + 8 bits of parity
Designing with FPGA Resources - 19

Copyright 2010 Xilinx

DQ
DQ

DI
A[1
3:0
]

DQ
Ram_ Extension
DQ
11

1
0

DI
DI

DO

A14
A14

DQ
DQ

WE
WE __ Control
Control

DQ
DQ

DI
DI

DQ
DQ

A[13:0]
A[13:0]

DQ
Ram_ Extension
DQ

1
0

A[13:0]
A[13:0]

(To
(ToInitiate
InitiateWrite
WriteOperation)
Operation)

Not Used
1
0

A14
A14

11

1
0

DQ
DQ

WE
WE __ Control
Control

(To
(ToInitiate
InitiateWrite
WriteOperation)
Operation)

Example: Cascade eight block RAMs to

build 256-kb memory

Virtex-6 FPGA FIFO18/36 Features

600-MHz maximum frequency

Synchronous or asynchronous read and write clocks
No phase relationship required in asynchronous mode

Four flags

DIN Bus
WREN

> WRCLK

RDEN

Full, empty, programmable almost full, and

programmable almost empty

Optional First Word Fall Through (FWFT)

> RDCLK

RESET

DOUT Bus
FULL
AFULL
EMPTY
AEMPTY
RDERR
WRERR
RDCONT<11:0>
WRDCONT<11:>

Immediate availability of the first word after empty

FIFO configurations
36-kb: 8k x 4, 4k x 9, 2k x 18, 1k x 36, 512 x 72
512 x 72 can implement Error Correcting Codes (ECC)

18-kb: 4k x 4, 2k x 9, 1k x 18, 512 x 36

No byte write enables

Both ports must be same width
Designing with FPGA Resources - 20

Copyright 2010 Xilinx

FIFO read port is block RAM Port A

FIFO write port is block RAM Port B

Virtex-6 FPGA FIFO Modes

1. Asynchronous clocks

Can be used in Standard or

FWFT mode
EN_SYN = FALSE (default)
DO_REG = 1
Assertion of flags are zero latency

2. Synchronous clocks

Can be used in Standard mode only

EN_SYN = TRUE
DO_REG = 0, 1

FIRST_WORD_FALL_THROUGH =
FALSE (default)

If DO_REG = 1, adds a pipeline stage to flags and outputimproving Tcko

All flags are zero latency

Designing with FPGA Resources - 21

Copyright 2010 Xilinx

Virtex-6 FPGA FIFOs are Cascadable

Flexible FIFO configuration
DIN<35:0>

No dedicated cascade logic

RDEN
WREN
RDEN

Expand width, depth, or

both using fabric
logic

DIN<71:36>
WREN

DIN<35:0> DOUT<35:0>
WREN
RDEN
EMPTY
WRCLK
AFULL
RDCLK

FIFO
FIFO
#1
#1

DIN<35:0> DOUT<35:0>
WREN
RDEN
EMPTY
WRCLK
AFULL
RDCLK

FIFO
FIFO
#1
#1

1kx72 FIFO
DIN<3:0>
WREN
WRCLK

DIN<3:0>

DOUT<3:0>

Data_Avail
WREN
Data_Taken
WRCLK
RDCLK

FIFO
FIFO
#1
#1

RDCLK
RDEN

DIN<3:0>

DOUT<3:0>

WREN
RDEN
WRCLK
RDCLK

DOUT<3:0>

AFULL

FIFO
FIFO
#2
#2

16kx4 FIFO

Depth Cascade
Designing with FPGA Resources - 22

Copyright 2010 Xilinx

Width Cascade

DOUT<35:O>
EMPTY

DOUT<71:36>

AFULL

Block RAM and FIFO Use

Inference of block RAM is possible
Specific coding techniques are required
Most block RAM capabilities are available
Dual port, individual clocks, separate read/write ports, output register, set/reset

See the XST Users Guide > RAMs and ROMs

Inference of FIFOs is not possible

Xilinx suggests that you use IP (CORE Generator & Architecture Wizard)

Designing with FPGA Resources - 23

Copyright 2010 Xilinx

IP (CORE Generator & Architecture Wizard)

Designing with FPGA Resources - 24

Copyright 2010 Xilinx

Lessons

I/O
Block RAMs and FIFO
DSP48 Resources
Other Features
Summary

Designing with FPGA Resources - 25

Copyright 2010 Xilinx

A:B

18

43
43

0
1

25
C

48

C
0

>>17

ACIN

BCIN

INMODE

Designing with FPGA Resources - 26

Copyright 2010 Xilinx

Carry

3
CarryInSel

30

25x18
25x18signed
signedmultiplier
multiplier
48-bit
48-bitadd/subtract/accumulate
add/subtract/accumulate
48-bit
48-bitlogic
logicoperations
operations
Pipeline
Pipelineregisters
registersfor
forhigh
highspeed
speed
Pattern
detector
Pattern detector
SIMD
SIMDoperations
operations(12/24
(12/24bit)
bit)
Cascade
Cascadepaths
pathsfor
forwide
widefunctions
functions
Pre-adder
Pre-adder

OpMode

>>17

18

48

48
P
2
PATTERN_
DETECT

PCIN

25

30

86 0

PATTERN

Dual A, D
Register
With
Pre-adder

CARRY
OUT

30

25 X 18

ALUMode

30
A

MULT
SIGNIN

48

PCOUT

CARRY
CASCOUT
MULT
SIGNOUT
18

Dual B
Register

18

CarryIn

18

CARRY
CASCIN

ACOUT

BCOUT

Virtex-6 FPGA DSP48E1 Slice

18

A0

A1

18

48

PCOUT

CCOUT

BCOUT

Spartan-6 FPGA DSP48A1 Slice

36

D:A:B

MFOUT

18

18

18

18 X 18

M
C

+/0

48

BCIN

OPMODE[6,4]

18

18x18
18x18signed
signedmultiplier
multiplier
48-bit
48-bitadd/subtract/accumulate
add/subtract/accumulate
Pipeline
Pipelineregisters
registersfor
forhigh
highspeed
speed
Cascade
Cascadepaths
pathsfor
forwide
widefunctions
functions
Pre-adder
Pre-adder

Designing with FPGA Resources - 27

Copyright 2010 Xilinx

48
P

48
CIN

12

PCIN

Dual B, D
Register
With
Pre-adder

OPMODE[7]

18

CFOUT

OPMODE[5]

36 0

OPMODE[3:0]

18

Virtex-6 FPGA Pre-Adder

Bitstream Controlled

The A input to multiplier is controlled by INMODE[3:0]

Dynamically selects A1/A2 pipeline level

Dynamically Controlled

Dynamically selects add/subtract

Dynamically selects Zero for A or D

30

ACOUT

30

X MUX

ACOUT and X MUX input are statically controlled

INMODE[1]

30

ACIN

A2

A1

25
INMODE[0]

A MULT
D
25

25

D
INMODE[2]

Designing with FPGA Resources - 28

INMODE[3]

Copyright 2010 Xilinx

AD

25

X, Y, and Z Multiplexers
Basic operations are
Z (X + Y + CARRYIN)

ALU_MODE = 0000 or 0011

-Z (X + Y + CARRYIN) 1 ALU_MODE = 0001 or 0010

X, Y, and Z multiplexers allow for dynamic OPMODEs

Multiplier output requires both X and Y multiplexers

Normal or 17-bit right shifted with

MSB fill for multi-precision
arithmetic

Designing with FPGA Resources - 29

Copyright 2010 Xilinx

Apply Your Knowledge

OPMODE
Controls the behavior of X, Y, and Z multiplexers

2) Given this OPMODE table,

what is the OPMODE for the
following functions?
C + A:B
A*B + C
P + C + PCIN
Designing with FPGA Resources - 30

Copyright 2010 Xilinx

Virtex-6 FPGA: Two-Input Logic Functions

ALUMODEs

48 bit logic operations

Logic Unit Mode

OPMODE[3:2]

ALUMODE[3:0]

X XOR Z

00

0100

X XNOR Z

00

0101

X XNOR Z

00

0110

X XOR Z

00

0111

X AND Z

00

1100

X AND (NOT Z)

00

1101

X NAND Z

00

1110

(NOT X) OR Z

00

1111

X XNOR Z

10

0100

X XOR Z

10

0101

X XOR Z

10

0110

X XNOR Z

10

0111

X OR Z

10

1100

X OR (NOT Z)

10

1101

X NOR Z

10

1110

(NOT X) AND Z

10

1111

XOR, XNOR, AND, NAND, OR,

NOR, NOT
ALUMODE[3:0]

0
P
A:B

0
1

0
PCIN
P
C

OPMODE[3:0]
Designing with FPGA Resources - 31

Copyright 2010 Xilinx

Virtex-6 FPGA: Pattern Detect and SIMD

Pattern detection
Pattern and mask operation on output of adder

Pattern can be constant (set by attribute) or C input

Enables

Symmetric rounding for multi-precision operations

Convergent rounding
Saturation
Accumulator terminal count

SIMD operations
48 bit adder broken into 2x24 bits or 4x12 bits
Allows two or four independent additions to be done

Carry bits brought out independently and

disabled between sections
Carry bits can be cascaded between DSP48E1
slices
Designing with FPGA Resources - 32

Copyright 2010 Xilinx

C or MC

Cascade Paths
Cascade paths exist from each DSP48 slice to the slice above it
A input, B input, P output and shifted P output, carry out

Enables common functions with little or no additional resources

Wider accumulators and multipliers, complex multipliers, and FIR filters, for
example

Example: 35bitx25bit Multiplier with two Virtex-6 FPGA DSP48E1s

25

DSP48_1
OPMODE 0010101
ALUMODE 0000

B[34:17]

18
ACIN

DSP48_0

A[24:0]
OPMODE 0000101
0,B[16:0]
ALUMODE 0000

Designing with FPGA Resources - 33

P[42:0] = OUT[59:17]

SHIFT 17

25

P
18

Copyright 2010 Xilinx

P[16:0] = OUT[16:0]

Implement or Accelerate DSP Functions

DSP Operation

Logic

Fast Fourier Transform (FFT)

Finite Impulse Response (FIR)
Infinite Impulse Response (IIR)
C Integer Comb (CIC)
Quadrature Filter
Decimating Filter
Interpolating Filter
Linear Phase Filter
CORDIC Functions
Butterworth Function
Chebyshev Function
Bessel Function
Forward Error Correction (FEC)
Pre-distortion
Encoding
Encryption
Compression

Designing with FPGA Resources - 34

Copyright 2010 Xilinx

DSP48

IP Support
IP (CORE Generator & Architecture Wizard)

IP is currently supported in the IP (CORE Generator and Architecture Wizard)

tool for the ISE software
A sampling of cores supported
Adder/Subtracter
CORDIC
Accumulator
Multiply and Accumulate (MAC)

Serial Divider
Filters (CIC and FFT)

Dynamic Control
MAC FIR

Transforms (DFT and FFT)

SIN COS LUT

MAD

DDS
Complex Multipliers

Designing with FPGA Resources - 35

Copyright 2010 Xilinx

Creative Uses of DSP48E1

If not needed for MACC functions, can be used to implement
48-bit 2-1 multiplexer
3-bit 6-1 multiplexer
And other N bit M-1 multiplexers where NxM 18

48 bit counter or multiple smaller counters

Many more...

Requires creative use of OPMODE and ALUMODE

Designing with FPGA Resources - 36

Copyright 2010 Xilinx

Lessons

I/O
Block RAMs and FIFO
DSP48 Resources
Other Features
Summary

Designing with FPGA Resources - 37

Copyright 2010 Xilinx

Gigabit Transceivers

TX

2
PMA PCS

RX

PMA

FPGA
Fabric
Interface

PCS

Dedicated parallel-to-serial transmitter and serial-to-parallel receiver

Unidirectional, differential bit-serial data I/O
Integrated PLL-based Clock and Data Recovery (CDR)

Parallel interface to the FPGA internal fabric

8 to 40 bit wide to accommodate internal speed limits and optional fabric encoding

Serial interface to the printed circuit board (differential signaling)

Differential Current Mode Logic (CML)
Two traces for the transmitter and two traces for the receiver; removes common-mode noise
Programmable signal swing and TX and RX equalization
Designing with FPGA Resources - 38

Copyright 2010 Xilinx

Virtex-6 FPGA GTX Transceiver Protocols

Datacom

Wireless
CPRI 6G, 2.5G, 1.2G, 614M
OBSAI 6G, 3G, 1.5G, 768M

1GbE
2.5GX (Broadcom 2.5GE)
XAUI
DDR XAUI (RXAUI)
10G-Base CX4
40GE (5.15Gbps interface to external MUX)
100GE (5.15Gbps interface to external MUX)

Computing

Video

Telecom

SONET OC-48
SONET OC-12
SONET OC-3 (with fabric oversampling)
OTU1
OTU4 (5.59Gbps interface to external MUX)
SFI-5.1
SFI4.2
GPON 2.488Gbps TX / 1.244Gbps RX with BCDR

Designing with FPGA Resources - 39

PCI Express technology Gen1 and Gen2 (to x8)

SRIO Gen1 and Gen2
InfiniBand
Intel QPI

SDI
HD-SDI
3G-SDI
Display Port
DVB-ASI

Storage

Copyright 2010 Xilinx

SATA
SAS
Fiber Channel

Chip-to-Chip

Interlaken
SPAUI
Aurora
OIF CEI-6SR

Spartan-6 FPGA GTP Transceiver Protocols

Datacom

Wireless

1GbE
XAUI (pending IP characterization)
10G-Base CX4 (pending IP
characterization)

CPRI 3G, 2.5G, 1.2G, 614M

OBSAI 3G, 1.5G, 768M

Computing
PCI Express Gen1 (Hard IP supports x1)
InfiniBand

Telecom
SONET OC-3 (with fabric oversampling
see DRU XAPP875)
SONET OC-12
SONET OC-48 (pending char until then,
requires ext. PHY)
OTU1 (pending char until then, requires
ext. PHY)

Video
Display Port
SDI (pending char - with fabric
oversampling, XAPP875)
HD-SDI (pending characterization)
3G-SDI (pending characterization)

Storage

Chip-to-Chip

SATA

Serial RapidIO
Aurora
Designing with FPGA Resources - 40

Copyright 2010 Xilinx

PCI Express Endpoint Block Key Features

Highly configurable hard PCI Express block
Supports endpoint and root port
Scalable bandwidth
Transaction
Transaction
Layer
Layer

1, 2, 4, or 8 lanes for both

Gen 1 and Gen 2 data rates

Data
Data Link
Link
Layer
Layer

Physical
Physical
Layer
Layer

Meets all key PCI Express technology

v2.0 requirements

Electrical signaling
Protocol (CRC, automatic retry)
Quality of Service (QoS)
Hot pluggable

GTX
GTX
GTX
GTX
GTX
GTX
GTX
GTX
GTX
GTX

Configuration
Configuration and
and Capabilities
Capabilities Module
Module

PCI Express Block

To
To Fabric
Fabric

Virtex-6 FPGA

Uses GTX transceiver blocks

Designing with FPGA Resources - 41

GTX
GTX
GTX
GTX
GTX
GTX

Copyright 2010 Xilinx

Virtex-6 FPGA Tri-Mode EMAC

Tri-mode 10 / 100 / 1000 Mb/s: full or half duplex
IEEE 802.3 compliant
Available in every LXT and SXT device

EMAC

Four integrated EMACs per chip

Programmable PHY interfaces

EMAC

Flexible support of both copper

and optical networks

EMAC
EMAC

New 2.5 Gbps over-clocking option

Designing with FPGA Resources - 42

Copyright 2010 Xilinx

Virtex-6 FPGA Tri-Mode EMAC

Statistics Interface

Supports legacy Virtex-5 FX FPGA feature set

Standard PHY interface support

Generic or Dynamic Configuration host (DCR)

DCR Bus

Receive EMAC address filter

Jumbo-frame support

Host Bus

Increased bandwidth with larger packets

Reduced host processing

Network traffic monitoring and filtering

Real time statistics for TX and RX

Up to four blocks per device

Designing with FPGA Resources - 43

Processor
Processor
Interface
Interface

Copyright 2010 Xilinx

TX
Stats Mx

EMAC Core

Host Interface

Phy Interface

Selectable host interface

Client Interface

RX
Stats Mx

MII, GMII, RGMII, SGMII

PCS/PMA for 1000BASE-X

Usage Models
Use the CORE Generator software to access all of these features
FPGA Features and Design > IO Interfaces
Standard Bus Interfaces > PCI Express
Communications & Networking > Ethernet

Designing with FPGA Resources - 44

Copyright 2010 Xilinx

Lessons

I/O
Block RAMs and FIFO
DSP48 Resources
Other Features
Summary

Designing with FPGA Resources - 45

Copyright 2010 Xilinx

Apply Your Knowledge

3) What is the easiest method for building resources such as I/O, memory, and
DSP functions?

Designing with FPGA Resources - 46

Copyright 2010 Xilinx

Summary
The IOB tile contains the IOB, ILOGIC/ISERDES, OLOGIC/OSERDES, and
IODELAY blocks
The ILOGIC and OLOGIC blocks provide SDR and DDR registers
The ISERDES and OSERDES blocks provide source-synchronous
capabilities utilizing dedicated resources
Block RAMs support various memory sizes in single-port, simple dual-port,
and true-dual port configurations
The Virtex-6 FPGA FIFO18 and FIFO36 blocks resources support
synchronous and asynchronous FIFOs
The DSP48 block provides maximum performance and low power for DSP
applications
Designing with FPGA Resources - 47

Copyright 2010 Xilinx