Floating Point MAC

Implementation Using Residue

Number System
Presented by:

Under the guidance of :

Mr.PRADEESH .K. P ,AMIE., M.Tech.
Asst.Proffeessor
Dept.of E&C
K.V.G.C.E,Sullia

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Floating Point Mac implementation Using

Residue Number System

ABHISHEK.M.S
4KV13LVS01
th
4 sem, M .Tech ( VLSI & ES)
K.V.G.C.E,Sullia

CONTENTS

Introduction
Proposed methodology
Residue number system
Binary to RNS Converter
RNS to binary converter
Advantages
Results
Conclusion
References

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Floating Point Mac implementation Using

Residue Number System

INTRODUCTION
As a result of the rapid advance in communication and multimedia systems, the
signal processing techniques are highly in demand.
The main components used in Digital signal processor (DSP) are multiplier,
adder and multiplier and accumulator (MAC) unit.
Residue number system gained popularity because of the parallel processing
and carry free arithmetic.

Fixed point number was inefficient for big number arithmetic and hence the
floating point arithmetic was invented.

In this design the input is in 16 bit floating point representation and the output
is in 32 bit floating point representation .

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Proposed Methodology

Figure1:Block diagram of floating point MAC unit

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Block diagram of floating point multiplier

Figure2:Block diagram of floating point multiplier

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Contd..
Floating point multiplication involves multiplication of
mantissa and addition of exponent
Floating point inputs are given as Mantissa and Exponent.
The unbiased Exponent is converted to biased to ensure that
the Exponent is unsigned.
The Mantissa and biased Exponent is converted to Residue
Number System. In RNS, based on the moduli, residues are
obtained.

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Contd..
For multiplication, the Mantissa should be multiplied and
Exponent should be added. For this, an RNS Mantissa modulo
multiplier and RNS Exponent modulo adder are used.
Using accumulator the products are added and saved.

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Floating Point Mac implementation Using

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Residue Number System

In recent times Residue Number System is becoming popular
because of its carry free addition and multiplication
capabilities. Since there is no carry propagation between
arithmetic blocks, high speed processing can be obtained.
RNS representation encodes large numbers into small
residues so that computation can be performed more
efficiently. The arithmetic can be implemented in parallel for
these residues. This ensures that there is no dependency
between each modulo unit. So, the complexity of the
arithmetic units in each modulo unit is reduced.

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Contd.
The MAC unit makes use the special Moduli set,{2^n1,2^n ,
2^n +1} that is taken to improve the performance of the unit.
By making use of these Moduli a particular binary number can
be converted into corresponding residues. This set of Moduli
makes the forward conversion process fast and simple.

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Binary to RNS Converter

Figure3:Block digram of Binary to RNS converter

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Contd..
The process of converting binary data into RNS is referred to as
the forward conversion. The n value is decided based on the
number of bits of the input binary number.
The forward conversion is done as follows:
b2= 2^(j-n)*xj where j=n to 2n-1
b1= 2^(j-2n)*xj where j=2n to 3n-1
b3= 2^(j)*xj where j=0 to n-1
Then the residues can be obtained as follows:
r1=(b1+b2+b3) %((2^n)-1)
r 2=b3
r3= (b1-b2+b3)%((2^n)+ 1)
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Contd..
2.5=1.010*2^-1
Exponent=00001(5 bits)
B1=0; B2=0; B3=1
r1=1; r2=1; r3=1

3.5=1.11*2^-1
again r4=1; r5=1; r6=1

Hence p1,p2,p3=2,2,2
Mantissa
2.5=>0100000000
B1=0; B2=1; B3=0

3.5=>1100000000
B3=0; B4=3; B5=0

r1=1;r2=0;r3=1

r4=3;r5=0;r6=3

Hence p4,p5,p6=3,0,3

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RNS to Binary converter

The conversion is done by using chinese remainder theorem and is also called as
reverse conversion.
Given a set of moduli {m1 ,m2 ,m3 ...mi } and the residues are {r1 r2,r3 , ... ri} ,
then binary number X is given as:
X=(Minv(i)*Mi*ri)%M; where i=1 t0 3;
Suppose we have three moduli set {m1 ,m2 ,m3} then,
M1=(m1*m2*m3)/m1;
M2=(m1*m2*m3)/m2;
M3=(m1*m2*m3)/m3
Now Minv (i) can be obtained from following equations
(Minv(1)*M1)%m1 =1;
(Minv(2)*M2)%m2=1;
(Minv(3)*M3)%m3 =1;
Where M=m1*m2*m3;

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Contd

n value in the moduli set (2^n-1,2^n,2^n+1)is selected depending up on the number

of bits in the inputs.
n=2 for exponent ;n=8 for mantissa

For exponent(2.5*-3.5) case:

M1=20;M2=15;M3=12
Minv(1)=2
Minv(2)=3
Minv(3)=3
M=3*4*5=60
ri=(p1,p2,p3=2,2,2)
Hence X=242%60=2

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For mantissa (2.5*-3.5) case:

M1=65792; M2=65535;M3=65280
Minv(1)=128
Minv(2)=255
Minv(3)=129
M=255*256*257=16776960
ri=(p4,p5,p6=3,0,3)
Hence X=50527488%16776960=196608

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ADVANTAGES

Less power
Less area
Less timing delay
Faster performance

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RESULTS
2.5*-3.5=-8.75
8.75=1.00011*2^-3
Mantisa=00011000000000000000000
Exponent=10000010
Sign bit=1

Figure 3:simulation results

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Synthesis Report

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Contd

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Contd
Comparison with a high performance mac unit shows that the
mac unit using rns consumes less timing delay with lesser
power consumption.
The proposed system consumes only 6% (1284out of 19200)
of the total area.
parameter

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Mac using rns

Mac with out rns

Time Delay(nsec) 2.678

5.246

Total Dynamic
power(mw)

27.29

0.018

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CONCLUSION
The floating point MAC unit designed using residue number
system performs the operations much faster with lesser timing
delay and area requirements.
The power report gives both the dynamic as well as quiescent
power whose summation gives the total power consumed by
the system.
The power consumption for the proposed system was also
found to be much lesser than the existing system.

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REFERENCES
[I] BehroozParhami, "Computer arithmetic-Algorithms and hardware designs", Oxford University
Press, 2000.
[2] sonali Mehta,Balwinder singh,Dilip kumar,performance analysis of floating point MAC
unitInternational journal of computer applications:volume 78-no.1,September 2013
[3] Ghosh, S. Singha, and A. Sinha, "Floating point RNS: a new concept for designing the MAC
unit of digital signal processor,"SIGARCH Comput Archit. News vol 40, no. 2, pp 39-43, May
2012.
[4] Shishir Kumar Das,aniruddhakanhe,R.H .Tawekar.design and implementation of high
performance mac unit,international journal of scietific engineering and research,volume 4,issue
6,june -2013
[5] M. Dugdale, "VLSI implementation of residue adders based on binary adders," Circuits and
Systems I I: Analog and Digital Signal Processing, IEEE Transactions on, vol. 39, no. 5, pp 325329, 1992.

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