Verification Presentation 1

Verification Training
Verification Methodology
System Verilog Fundamentals
7/16/15
Content
Data types, procedural statements and routines in
System Verilog
Basic OOP and connecting test bench to the DUT
System Verilog Assertion SVA
Randomization in System Verilog
Advanced OOP, thread and inter process
communication
Dolphin Technology Inc.
Methodology, Data types,

Procedural statements
and Routines
7/16/15
Content
System Verilog Fundamentals
Data types
Procedural statements and routines
ASIC design
Functional verification need
Test bench
Self-checking test bench
Does a design work and how is it done?
Code coverage
Functional coverage
Coverage driven constraint random verification

architecture
Verification plan and phases of verification
ASIC design
Functional verification need

Why we need functional verification?
To build confidence and stay in business.
A primary purpose for functional verification is to detect failures so that
bugs can be identified and corrected before it gets shipped to
costumer.
Testbench
Linear Testbench.
+ Instantiate the design under test (DUT)
+ Stimulate the DUT by applying test vectors.
+ Output results waveform window or to a terminal for visual
inspection manually.
Flat testbenh: they probably looked like the low-level code, all in
one file.
Layered testbench : dividing the code into smaller pieces
Self-checking test bench
Code coverage
Statement coverage: also known as line
coverage. This is required to be 100% for every
project.
Block coverage: The block coverage considers
branched blocks of if/else, case branches, wait,
while, for etc.
Conditional coverage: also called as expression
coverage, will reveals how the variables or subexpressions in conditional statements are
evaluated.
Brand coverage: reports the true or false of the
conditions like if-else, case and the ternary
operator (? :) statements in every branch.
Code coverage (Cont)

Path coverage is considered to be more complete
than branch coverage because it can detect the
errors related to the sequence of operations.
Analysis of path coverage report is not so easy
task.
Code coverage (Cont)

Toggle coverage: It makes assures that how
many times variables and nets toggled.
FSM coverage: It is the most complex type of
code coverage.
We look for how many times states are visited,
transited and how many sequence are covered in a
Finite state machine.
Functional coverage
SystemVerilog provides a mechanism to know
the untested feature using functional coverage.
Summary of functional coverage advantages:
+ Functional coverage helps determine how
much of your specification was covered.
+ Functional coverage qualifies the testbenchs.
+ Considered as stopping criteria for unit level
verification.
+ Gives feedback about the untested features.
+ Gives the information about the redundant
tests which consume valuable cycle.
+ Guides to reach the goals earlier based on
grading.
Coverage driven constraint random
14
Coverage driven constraint random

Generators create inputs at a high level of
abstraction namely, as transactions like read write
operation. The drivers convert this input into actual
design inputs, as defined in the specification of the
designs interface.
Monitor reports the protocol violation and identifies
all the transactions.
Scoreboard is sometimes referred as tracker.
Scoreboard stores the expected DUT output.
Environment contains the instances of all the
verification component.
15
Phases of verification
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Verification Plan
The Verification Plan
is the focal point for defining exactly what needs to be tested,
and drives the coverage criteria.
Verification Plan Contains The Following:

Overview
Resources, Budget and Schedule
Verification Environment
System Verilog Verification Flow
Feature Extraction
Stimulus Generation Plan
Checker Plan
Coverage Plan
Details of reusable components
17
4-state and 2-state data types

4 state data type: (0,1,X,Z)
Logic , wire . . .
Interger, time . . .
2 state data type: (0,1)

Byte, shortint, int, longint, bit . . .
Signed and unsigned
18
Fixed-Size Arrays
Declaring:
int fix_arr1[0:15]
bit fix_arr2[7:0][3:0]
bit fix_array3[8][4]
Packed vs Unpacked
PackedUnpacked
19
Fixed-Size Arrays
Initializing:
int fixed_arr[5];
fixed_arr = {0,1,2,3,4};
fixed_arr[0:2] = {7,6,5};
fixed_arr = {4{5}};
fixed_arr = {defaut:42};
Array Operator:
For
Foreach
int array[0:4];
for (int i =0;i<=4;i++); = foreach(array[i]);
20
Dynamic array
Declaring:
integer dyn_arr_1[], dyn_arr_2[];
interger multi_d_dyn_arr[][];
Initializing:
dyn_arr_1 = new [4];
//allocate 4 element
dyn_arr_1 = {0,1,2,3,4};
dyn_arr_2 = dyn_arr_1;
// copy a dynamic array
dyn_arr_1 = new[20](dyn_arr_1);// allocate 20 element and
copy
Dyn_arr_1.delete;
21
Queue
A queue is a variable-size, ordered collection of
homogeneous elements.
A Queue is analogous to one dimensional
unpacked array that grows and shrinks
automatically.
Queues can be used to model a last in, first out
buffer or first in, first out buffer
22
Queue
Operator:
int q[$] = { 2, 4, 8 };
int p[$];
int e, pos;
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q[0] = e; // write the first item
p = q; // read and write entire queue (copy)
q = { q, 6 }; // insert '6' at the end (append 6)
q = { e, q }; // insert 'e' at the beginning (prepend e)
q = q[1:$]; // delete the first (leftmost) item
q = q[0:$-1]; // delete the last (rightmost) item
q = q[1:$-1]; // delete the first and last items
q = {}; // clear the queue (delete all items)
q = { q[0:pos-1], e, q[pos,$] }; // insert 'e' at position pos
q = { q[0:pos], e, q[pos+1,$] }; // insert 'e' after position pos
23
Queue
Method
The size() method returns the number of items in the queue. If
the queue is empty, it returns 0.
The insert() method inserts the given item at the specified
index position.
The delete() method deletes the item at the specified index.
The pop_front() method removes and returns the first
element of the queue.
The pop_back() method removes and returns the last
element of the queue.
The push_front() method inserts the given element at the
front of the queue.
The push_back() method inserts the given element at the end
of the queue.
24
Queue
byte qu [$] ;
qu.push_front(2);
qu.push_front(12);
qu.push_front(22);
qu.push_back(11);
qu.push_back(99);
Answer: 22 12 2 11 99
25
Assciative Arrays
data_type array_id [ key _type];
data_type is the data type of the array elements.
array_id is the name of the array being declared.
key_type is the data-type to be used as an key.
Example:
int array_name[*]; //Wildcard index. can be indexed by any
integral datatype.
int array_name [ string ]; // String index
int array_name [ some_Class ]; // Class index
int array_name [ integer ]; // Integer index
typedef bit signed [4:1] Nibble;
int array_name [ Nibble ];
// Signed packed array

26
Assciative Arrays
Methods
num() or size()method returns the number of entries in
the associative array.
delete() method removes the entry at the specified
index.
exists() function checks whether an element exists at
the specified index within the given array.
first() method assigns to the given index variable the
value of the first (smallest) index in the associative array.
It returns 0 if the array is empty; otherwise, it returns 1.\
27
Assciative Arrays
last() method assigns to the given index variable the
value of the last (largest) index in the associative array. It
returns 0 if the array is empty; otherwise, it returns 1.
next() method finds the entry whose index is greater
than the given index. If there is a next entry, the index
variable is assigned the index of the next entry, and the
function returns 1. Otherwise, the index is unchanged,
and the function returns 0.
prev() function finds the entry whose index is smaller
than the given index. If there is a previous entry, the
index variable is assigned the index of the previous
entry, and the function returns 1. Otherwise, the index is
unchanged, and the function returns 0.
28
Linked list
Linked list: is defined as a parameterized class,
meaning that it can be customized to hold data of
any type.
Container: are objects that contain and manage other
objects
Iterator: provide the interface to containers.
are pointers to nodes within a list
`include <List.vh>
List#(integer) il;
List_Iterator#(integer) itor;
29
Linked List
`include <List.vh>
module lists();
List#(integer) List1;
List_Iterator#(integer) itor;
initial begin
List1 = new();
List1.push_back(10);
List1.push_front(22);
List1.pop_front();
List1.pop_front();
List1.push_back(5);
itor = List1.start();
itor.next();
itor.next();
itor.next();
itor = List1.erase(itor);
end
endmodule
30
Array Methods
sum, product
and or xor
min max unique find
reverse sort rsort - shuffle
31
Compare
Flexibility:
Choose a fixed-size array if the array size is known at
compile time
Choose a dynamic array if the array size is not known
until run time
Choose associative arrays for nonstandard indices such
as widely separated values because of random values or
addresses
Choose queues or linked list are a good way to store
values when the number of elements grows and shrinks
a lot during simulation
32
Compare
Speed:
Fixed-size array, dynamic array : fastest because
elements are stored in contiguous
Queue: not fast if Inserting or removing elements in the
middle
Linked list: not fast if Inserting or removing elements in
the middle
associative array: slowest and increase with size of array
33
Compare
Size
Fixed-size, dynamic array: good if array has a thousand
to a million elements
Queue: if your data set grows and shrinks often
Associative array: good if array has larger than a few
megabytes
Linked list: not good if array size is big
34
User-defined data types with typedef
Create new types using the typedef statement

Syntax: typedef type name
Eg: typedef logic [1:0] opreg_t
Define uint: typedef bit [31:0] uint;
35
User-defined data structure

A struct groups data fields together.
Creating a Struct and a New Type
struct {bit [7:0] r,g,b;} pixel;
typedef struct {bit [7:0] r,g,b;} pixel_s;
Initializing a Structure: using `{value1, value2};

Packed Structures: A packed structure is stored as
a contiguous set of bits with no unused space.
36
Enumerated Types
An enumerated type allows you to create a set of
related but unique constants such as states in a state
machine or opcodes.
Eg : enum {red, blue, green} color;
You can get the string representation of an
enumerated variable with the built-in function name()
Defining Enumerated Values: The actual values
default to intstarting at 0 and then increase.
Provides several functions: first, last, next, prev
The default type for an enumerated type is int(2state).
37
Constants
Parameter: In SystemVerilog, parameters can be
declared in a package so they can be used across
multiple modules.
Const
Eg : parameter A = 10;
Const byte colon = :;
38
Strings
An individual character is of type byte. The
elements of a string of length N are numbered 0 to
N-1.
The character \0 is ignored because memory for
strings is dynamically allocated.
Provide several function: getc(N), toupper(),
tolower(), putc(M,C), substr(start,end),
s1.compare(s2)
39
Expression width
Expression width depends on context.
bit [7:0] b8;
bit one = 1b1;
$displayb (one + one);
//0
b8 = one + one;
//2
$displayb(b8);
$displayb(one + one + 2b0);
$displayb(2(one) + one);
//2
//2
40
Procedural Statements and Routines

Procedural Statements:
SystemVerilog adopts many operators and statements
from C and C++.
a for loop, ++, -- operators, +=,=,=
If you have a label on a begin or fork statement, you can
put the same label on the matching end or join
statement.
Two new statements help with loops: continue, break.
Case () inside
41

Tasks, Functions, and Void Functions
The most important difference is that a task can
consume time whereas a function cannot.
A function cannot have a delay, #100, a blocking
statement such as @(posedge clock) or wait
(ready), or call a task (except in a thread spawned
with the fork join_none statement).
Void function does not return a value.
Default Value for an Argument.
Passing Arguments by Name (.port(a))
42

Returning from a Routine: return;
Automatic Storage: In SystemVerilog, routines still
use static storage by default, for both modules and
program blocks, use automatic storage by putting
the automatic keyword in the program statement.
Variable Initialization: Declare the initializing
program as automatic and never initializing a
variable in the declaration.
Time Values: ` timescale, timeunit and
timeprecision
Time, realtime variables.
43
Basic Object Oriented

Programming
7/16/15
Content
OOP brief
Object creation
Object de-allocation
Static and global variables
Class routines
Defining routines outside of the class
Using one class inside another
Dynamic objects
Copying object
Public and private
45
OOP Brief
Procedural programming (Verilog, C,)
Data structures (types) and the code (algorithms)
that uses them, are often separate in different files
=> Difficult to understand the functionality of a
program
There are no structures, only bit vectors and arrays
=> Limited in modeling and organizing data
The arrays are all static
=> Less flexibility and compatibility
46
OOP Brief
OOP - Object Oriented Programming
Create complex data types and tie them together
with the routines that work with them
Create testbenches and system-level models by
calling routines to perform an action
Working at a higher level, code is more easily
written and understood
More robust and easier to maintain and reuse on
future projects
47
OOP Brief
Terminology
Class
Object
Handle
Attribute
Method
Inheritance
Encapsulation
Abstraction
Polymorphism
etc
48
OOP Brief
Class
Contains data and codes with behavior
Describes all the properties, behavior, and identity
of objects
Object
An instance of class with behavior, identity
Expressed by the variable and methods
49
OOP Brief
Handle
A pointer to an object
Attribute
A variable that holds data
Method
Procedural code that manipulates variables, are
tasks and functions
Define the abilities and behaviors of an object
50
OOP brief
Example
Attribute
Method
Handle
Object
51
Object Creation
Declare a handle
Transaction tr;
tr points to an object of type Transaction,
initialized to the special value null
Can refer to many objects, but only one at a time
Construct a object
tr = new();
Allocates space for the Transaction
Initializes the variables to their default value
Returns the address where the object is stored
52
Object Creation
new() function
Making an instance of the class
For every class, SystemVerilog creates a default
new function to allocate and initialize an object
Custom constructor
53
Object Creation
Allocating multiple objects
Using objects
54
Object Deallocation
Long simulation might run out of memory
When a object is no longer use, should reclaim the
memory
Garbage collection is the process of automatically
freeing objects that are no longer referenced
When the last handle no longer references an
object, SystemVerilog releases the memory for it
55
Class Methods
Just a task
or function
defined
inside the
scope of
the class
56
Defining Methods Outside of the Class

Class scope resolution operator :: should be used
add the extern keyword at the beginning while
defining
57
Static Variables vs. Global Variables

Simple Static Variable
SystemVerilog allow to create a static variable inside a
class.
Shared amongst all instances of the class, but its scope is
limited to the class
58

Accessing Static Variables
Using a handle
Using class name followed by ::
Global
Visible to the entire testbench
59

Static Methods
Read and write static variables
60
Using One Class Inside Another

A class can contain an instance of another class,
using a handle to an object
The outer class can refer to things in the inner

class using syntax .
61
Using One Class Inside Another

Compilation Order
Declare the class name with a typedef statement
before use.
62
Dynamic Objects
In Verilog, every signal has a unique variable
associated with it
In OOP, there can be many objects, but only a few
named handles to manipulate them
Flexibility in allocate and de-allocated to save
memory in storing objects and during a simulation
63
Dynamic Objects
Passing Objects and Handles to Methods
64
Dynamic Objects
Modifying a Handle in a Task
Using ref on method arguments
SystemVerilog passes the address of the variable
so the method can modify it
65
Dynamic Objects
Modifying Objects in Flight
Need to create a new object for each transaction in
the testbench
66
Dynamic Objects
Arrays of Handles
The array made of handles, not objects
Need to construct each object in the array before
using it
Can not call new on an entire array of handles
67
Copying Objects
Copying an Object with the New Operator
Memory for the new object is allocated
all variables from the existing object are copied
68
Copying Objects
Any new() function that have defined is not called
69
Copying Objects
Writing Your Own Simple Copy Function
If class that does not contain any references to
other classes
70
Copying Objects
Writing a Deep Copy Function
If class that contain any references to other classes
71
Public vs. Local

In SystemVerilog, everything is public unless
labeled local or protected
Variables are kept local to the class by default to
keep one class from poking around inside another.
A class provides a set of accessor methods to
access and modify the data
Public: Everyone can see it, can be accessed by
any object of this class.
Local: Only the class in which it is declared can
see it (Can only be used in the methods of this
class)
72
Connect the test bench to

DUT
Separating the test bench and
design
The interface construct
Stimulus timing
Interface driving and sampling
Separating the test bench and design

The communication between blocks of a digital system is a
critical area. For large modules, this is not productive as it
involves.
Manually connecting hundreds of ports may lead to errors.

Detailed knowledge of all the port is required.
Difficult to change if the design changes.
More time consuming.
Most port declaration work is duplicated in many modules.
74
Separating the test bench and design

Example:
module Dut (input clk, read, enable,
input [7:0] addr,
output [7:0] data);
....
assign data = temp1 ? temp2 : temp3 ;
always @(posedge clk)
....
endmodule
module Testbench( input clk,

output read, enable,
output [7:0] addr,
input [7:0] data );
endmodule
module top();
reg clk;
wire read, enable;
wire [7:0] addr;
wire [7:0] data;
Dut D
(clk,read,enable,Addr,data);
Testbench TB(clk,read,enable,Addr,data);
endmodule
75

SystemVerilog added a new powerful features called
interface. Interface encapsulates the interconnection and
communication between blocks.
Interface declaration for the above example:

interfaceintf#(parameterBW=8)(inputclk);
logicread,enable;
logic[BW-1:0]addr,data;
endinterface:intf
76

DUT and Testbench modules using the above declared interface:
module Dut (intf dut_if);
assign dut_if.data = temp1 ? temp2 : temp3 ;

always @(posedge dut_if.clk)
endmodule
module Testbench(intf tb_if);
endmodule
module top();
bit clk;
initial
forever #5 clk = ~clk;
intf bus_if(clk);
Dut d(bus_if);
Testbench TB (bus_if);
endmodule
77

Connecting Interfaces and Ports
module top();
bit clk;
initial
forever #5 clk = ~clk;
intf bus_if(clk);
Dut d(
.clk
(clk),
.read
(bus_if.read),
.enable
(bus_if.enable),
.addr
(bus_if.addr),
.data
(bus_if.data) );
Testbench TB (bus_if);
endmodule
78

Grouping Signals in an Interface Using Modports
The modport construct in an interface lets you group
signals and specify directions.
interfaceintf(inputclk);
logicread,enable,
logic[7:0]addr,data;
modportdut (input read,enable,addr,
outputdata);
modporttb (output read,enable,addr,
inputdata);
endinterface:intf
moduletop();
logicclk;
intf
bus_if(clk);
Dut
d(bus_if.dut);
Testbench TB(bus_if.tb);
endmodule
79
Stimulus timing
- The timing between the testbench and the design should be
maintained to avoid race conditions.
80
Stimulus timing
Clocking block:
Identify clock signals, and captures the timing and
synchronization requirements of the blocks being
modeled.
Assembles signals that are synchronous to a
particular clock, and makes their timing explicit.
Clocking blocks can only be declared inside a
module, interface or program.
81
Stimulus timing
A testbench can contain one or more clocking
blocks.
Example interface use clocking block.
82
Stimulus timing
Referencing signals in the Clocking Block
Default input and default output in clocking block
83
Stimulus timing
Skew:
Input skew is specified then the signal is sampled at skew
time units before the clock event.
Output skew is specified, then output (or inout) signals are
driven skew time units after the corresponding clock event.
84
Stimulus timing
Skew can be specified in 3 ways:
#d: The skew is d time units.
#dns: The skew is d nano seconds.
#1step: specifies that signals be sampled in the postpone
region before any design activity.
If skew is not specified, default input skew is 1step and
output skew is 0.
85
Stimulus timing
Signal Synchronization:
Synchronize to active clock edge
Synchronize to any edge of signal
Wait for N clock cycles with ##n
86
SystemVerilog Assertion
Verification Training
7/16/15
SystemVerilog Assertion Terminology

Concurrent
Assertions
- Based on clock cycles
-Test expression is evaluated at clock edges based on the sampled values of
the variables involved.
- Placed in a procedural block, a module, an interface or a program
definition.
a_cc: assert property( @( posedge clk ) not
( a && b ) ) ;
88
SystemVerilog Assertion Terminology

Immediate Assertions
Based on simulation event semantics
Have to be placed in a procedural block definition.
always_comb
begin
a _ i a : assert (a
&& b ) ;
end
89
SVA Building Block
SystemVerilog Assertion
Checker
90
Sequence Assertion
sequence
name_of_sequence;
<test expression>;
endsequence
Sequence with edge definitions
Srose {boolean expression or
signal name)
$fell ( boolean expression or
signal name)
sequence s2 ;
@(posedge elk)
$rose(a) ;
endsequence
$stable {boolean expression or

signal name)
91
Sequence Assertion
Sequences with timing
relationship
sequence s4 ;
@( posedge clk ) a ##2 b;
endsequence
Success: start at 5, end at

7;
start at 14, end at 16;
92
Property Assertion
Syntax:
property name_of_property;
<test expression>; or
< complex sequence
expression>
endproperty
assertion_name: assert property
(property_name);
Forbidding a property
sequence s6;
@ (posedge clk) a ##2 b;
endsequenee
property p6;
not s6;
endproperty
a6 : assert property(p6) ;
93
Property Assertion
property p7;
@ (posedge clk) a ##2 b;
endproperty
a7 : assert property(p7)
$display("Property p7
succeeded\n") ;
else
$ display (" Property p7 failed \ n
");
Implication operator
Overlapped implication
Non-overlapped implication
94
Property Assertion
Implication operator
Overlapped implication
property p8 ;
@(posedge clk) a
|-> b;
endproperty
a8 : assert
property(p8) ;
95
Property Assertion
Implication
operator
Non-overlappedproperty p9 ;
implication
@(posedge clk) a |
= > b;
endproperty
a9 : assert property
(p9) ;
96
SVA constructs
$past (signal_name, number of clock
cycles)
property p19;
@(posedge clk) ( c && d ) |->
($past((a&&b) , 2) == 1b1) ;
endproperty
a19: assert property (p19) ;
97
Connecting SVA to the Design

Two different methods:
1. Embed or in-line the checkers in the module definition.
2. Bind the checkers to a module, an instance of a module
or multiple instances of a module
module inline (clk, a, b, d1, d2 , d ) ;

input logic clk, a, b;
input logic [7:0] d1, d2;
output logic [7:0] d;
always @( posedge clk )
begin
if (a)
d <= dl;
if (b)
d <= d2 ;
end
property p_mutex;
@ (posedge clk) not (a && b ) ;
endproperty
a_mutex: assert
property(p_mutex) ;
endmodule
98
Connecting SVA to the Design

Two different Methods:
1. Embed or in-line the checkers in the module definition.
2. Bind the checkers to a module, an instance of a module
or multiple instances of a module
module inline (clk, a, b, d1,
d2 , d ) ;
module mutex_chk(a, b, clk) ;
input logic clk, a, b;
input logic a, b, clk;
input logic [7:0] d1, d2;
property p_mutex;
output logic [7:0] d;
@(posedge clk) not (a &&
always @( posedge clk )
b) ;
begin
endproperty
if (a)
a_mutex: assert property
d <= d1;
(p_mutex) ;
if (b)
endmodule
d <= d2 ;
bind <module_name or instanceendmodule
name> <checker name>
<checker instance name> <design signals>;
bind inline mutex_chk i2 (a,
b, elk) ;
99
SVA for functional coverage

Functional coverage is a metric for measuring
verification status against
design specification.
Two categories:
a. Protocol coverage.
b. Test plan coverage
<cover_name> : cover
property(property_name)
c_mutex: cover property
(p_mutex) ;
Result:
1. Number of
attempted.
2. Number of
3. Number of
4. Number of
vacuously.
times the property was

times the property succeeded.
times the property failed.
times the property succeeded
100
SVA Simulation Methodology

Block level verification
-simulations are smaller and hence the bugs can be traced easily
and fixed promptly
SVA in design
blocks: Tips
All SVA checks written for a block level design

should be inlined.
The inclusion of SVA checks written at the block level
should be
controlled by a parameter defined within the design
module.
101
SVA Simulation Methodology

System level verification
Tips:
At the system level, a new set of assertions should be
written that
verifies the connectivity of the system.
More focus should be on
the interface rules rather than the internal block details.
102
Randomize
7/16/15
Randomization in SystemVerilog
Simple
Class with Random Variables
class Packet;
rand bit [3:0] src,dst;
randc bit [2:0] kind;
constraint c {src>2;
src<11;}
endclass
program main;
Packet p;
initial begin
p = new();
repeat(9)
begin
void'(p.randomize());
$display("src =%d ,dst= %d, kind = %d",
p.src, p.dst, p.kind);
end
end
endprogram
Result
#src = 3 ,dst=
5
# src = 3 ,dst=
=0
# src =10 ,dst=
=1
# src = 3 ,dst=
=6
# src =10 ,dst=
=7
# src = 3 ,dst=
=2
# src = 3 ,dst=
=4
# src =10 ,dst=
=3
# src = 3 ,dst=
=3
9, kind =
4, kind
2, kind
12,kind
3, kind
7, kind
0, kind
4, kind
14,kind
104
Checking the Result from Randomization
class Packet;
randc bit [2:0] kind;
constraint c {src>3;
src<2;}
endclass
program TestResult;
Packet p;
initial begin
p = new();
if (p.randomize())
$display("VALID RANDOM");
else
$display("INVALID RANDOM");
end
endprogram
result
INVALID RANDOM
=> The
randomizefunction returns
0 if a problem is found
with the constraints
105
What can be Randomized?

SystemVerilog allows you to randomize integral
variables
2-state and 4-state types, though randomization
only generates 2-state values
Cannot have a random string, or refer to a
handle in a constraint
Randomizing real variables is not yet defined in
the LRM
106
Constraint Details
Simple Expresions
Repair:
Bad ordering constraint
class Order_good;
class Order_bad;
rand bit [7:0] lo, med,hi;
rand bit [7:0] lo, med,hi;
constraint bad {lo < med < hi;} constraint good {lo < med;
med < hi;}
endclass
endclass
result
lo = 20 , med = 224, hi = 164
lo = 114, med = 39 , hi = 189
lo = 186, med = 148, hi = 161
lo = 214, med = 223, hi = 201
107
Constraint Details
Weighted Distributions
changing distribution
Weight random distribution with Dynamically
dist
weights
class Transaction;
class BusOp;
typedef enum {BYTE,WORD,LWRD}
constraint c_dist {
src dist {0:= 40, [1:3] := 60}; length_e;
rand leght_e len;
// src = 0 , weight = 40/220
bit [31:0] w_byte =1, w_word
// src = 1 , weight = 60/220
// src = 2 , weight = 60/220 =3,w_lwrd =5;
contraint c_len {
// src = 3 , weight = 60/220
len dist {BYTE
:= w_byte;
WORD := w_word;
dst dist {0:/40, [1:3] := 60};
LWRD := w_lwrd;};
// dst = 0, weight = 40/100
}
// dst = 1, weight = 20/100
endclass
// dst = 2, weight = 20/100
// dst = 3, weight = 20/100
}
endclass
108
Constraint Details
Set Membership and the Inside Operator

class Ranges;
rand bit [31:0] c;
bit [31:0] lo,hi;
contraint c_range {
c inside {[lo:hi]};
// lo <= c
&& c <= hi
// ! c inside {[lo:hi]} // c < lo or c
> hi
}
endclass
109
Constraint Details
Using an Array in a set

Random set constraint for an array
class Fib;
rand bit [7:0] f;
bit [7:0] val[] = '{1,2,3,5,8};
constraint c_fibonacci {
f inside vals;
}
110
Constraint Details
Bidirectional Constraints
Bidirectional constraints
class Birdir;
rand bit [15:0] r,s,t;
constraint c_bidir { // all are
solved in parallel
r < t;
// A value for r
affect s,t
s == r;
t < 10;
s >5 ;
}
endclass
111
Constraint Details
Implication Constraints
The expression A->B is equivalent to the
expression (! A || B)
Ex:
class LogImp;
rand bit d,e;
constraint c {
(d == 1) -> (e ==1);
}
endclass
=> when d==1, the variable
e must be 1, but when e==1,
d can be 0 or 1
112
Constraint Details
Implication Constraints
An if-else implication constraint
class BusOp;
rand operand_e op;
rand length_e len;
constraint c_len_rw {
if (op == READ) {
len inside {[BYTE:LWRD]};
else {
len == LWRD;
}
}
endclass
113
Constraint Details
Equivalence Operator
The equivalence operator <->is bidirectional. A<>Bis defined as ((A>B) && (B->A))
Ex:
rand bit d,e;
constraint c {d == 1} <-> (e ==
1);
=>}When dis true, emust also be true, and
when dis false, emust also be false
114
Solution Probabilities
Unconstrained
Implication
class Imp1;
class unconstrained;
rand bit x;
rand bit x;
// 0 or 1
rand bit [1:0] y;
rand bit [1:0] y; // 0 ,1,2 or 3
constraint c_xy {
endclass
(x == 0) -> (y == 0);
}
115
Implication and Bidirectional Constraint

class Imp2;
rand bit x;
rand bit [1:0] y;
constraint c_xy {
y >0;
(x == 0) -> (y == 0);
}
endclass
116
Guiding Distribution with Solve .. Before

class SolveXBeforeY;
rand bit x;
// 0 or 1
rand bit [1:0] y;
// 0,1,2 or 3
constraint c_xy {
(x == 0) -> (y == 0);
solve x before y;
}
endclass
117
Control Multiple Constrains

Syntax:
Control a single constrain
handle.constrain.constrain_mode(arg)
Control all constrain
handle.constrain_mode(arg)
arg = - 0 : constrain is turned off
- 1 : constrain is turned on
118
Control Multiple Constrains

Example :
class rand_mode;
rand integer Var1;
rand integer Var2;
constraint Var_1 { Var1 == 20;}
constraint Var_2 { Var2 == 10;}
endclass
program rand_mo_p_38;
rand_mo obj = new();
initial
begin
obj.randomize();
$display(" Var1 : %d Var2 : %d ",obj.Var1,obj.Var2);
obj.constraint_mode(0); //Both constraints Var_1 and Var_2 are turned off.
obj.randomize();
obj.constraint_mode(1); //Both constraints Var_1 and Var_2 are turned on.
obj.randomize();
end
endprogram
Var1 : 20 Var2 : 10
Var1 : 733126180 Var2 : -119008195
Var1 : 20 Var2 : 10
119
In-Line Constraints
Inline constraints allows to add extra constraints to already existing
constraints which are declared inside class.
Syntax : using randomize with
Example
class inline;
rand integer Var;
constraint default_c { Var > 0 ; Var < 100;}
endclass
program inline_test;
inline obj;
initial
begin
obj = new();
repeat(2)
if(obj.randomize() with { Var == 50;})
$display(" Randodmize sucessful Var %d
",obj.Var);
else
$display(" Randomization failes");
end
endprogram
# Randodmize sucessful
Var 50
# Randodmize sucessful
Var 50
120
Pre_randomize and Post_randomize

When randomize() is called,it first invokes the pre_randomize() then
randomize() finally if the randomization is sucesusful only
post_randomize is invoked.
Example:
program pre_post_test;
class simple;
function void pre_randomize;
$display(" PRE_RANDOMIZATION ");
endfunction
function void post_randomize;
$display(" POST_RANDOMIZATION ");
endfunction
endclass
simple obj = new();
initial
obj.randomize();
endprogram
# PRE_RANDOMIZATION
# POST_RANDOMIZATION
121
Random Number Functions

In System Verilog, we have some random functions
$random Flat distribution, returning signed 32-bit random
$urandom Flat distribution, returning unsigned 32-bit random
$urandom_range Flat distribution over a range
Example :
a = $urandom_range(3,10); //Pick a value from 3 to 10
b = $urandom_range(5); // Pick a value from 0 to 5
122
Constraints Tips and Techniques
Constraints with Variables

Using Nonrandom Values
Checking Values Using Constraints
Randomizing Individual Variables
123

Constraints with Variables
To make constrains more readable and flexiable
class Packet;
rand bit [31:0] length;
bit [3:0] max_length =100;
constrain c_length {
length inside {[1:max_length]}
}
endclass
124

Using Nonrandom Values
If there are just a few random variables that you want to override, use the
rand_mode function to make them nonrandom
class Packet;
rand bit [7:0] length, payload[];
constrain c_valid { length > 0; payload.size() = length;}
function void display (input string msg)
endfunction
endclass
Packet p;
Initial begin
p = new();
p.randomize();
p.display( simple randomization);
p.length.rand_mode(0);
p.length = 40;
p.randomize();
p.display (randomization with rand_mode);
end
125

Checking Values Using Constraints
When randomize() method is called by passing null, randomize() method
behaves as checker instead of random generator. It evaluates all the
constraints and returns the status.
class Eth_rx;
rand integer Pkt_len;
rand integer Var;
constraint var_c { Var < 1518 ;Var > 64 ;}
endclass
program Eth_test;
Eth_rx rx = new();
initial
begin
rx.Pkt_len = 32;
rx.Var = 871;
if(rx.randomize(null))
$display(" VALID PKT IS RECIVED ");
else
$display(" INVALID PKT IS RECIVED ");
end
endprogram
# VALID PKT IS RECIVED
126

Randomizing Individual Variables
To randomize the subset of variables, we can pass the argument to
randomize().Only those variables passed in the argument list will be
randomized; the rest will be treated as state variables and not randomized
class Rising;
bit [7:0] low;
rand bit [7:0] med, hi;
constrain up { low < med ;
med < hi;}
endclass
initial begin
Rising r;
r = new();
r.randomize(); // random all variable
r.randomize(med); //only med is randomized
r.randomize(low); //random only low through it isnt rand
end
127
Common Randomization Problems

Use Signed Variables with Care
Dont use int, byte or other signed type unless
if you really want signed value.
Example:
class Vars;
rand byte var1, var2;
constraint total {
var1 + var2 == 64;
}
endclass: Vars
//You could get pairs of values such as
(-63, 127)
128

Use Signed Variables with Care (cont)
Solve: use unsigned random variables and make
them as wide as needed.
Example:
class Vars;
rand bit [5:0] var1, var2;
constraint total {
var1 + var2 == 6d64;
}
endclass: Vars
129

Choose the Right Arithmetic Operator to
Boost Efficiency
Example:
rand bit [31:0] addr;
constraint c {
addr % 4096 inside {[0:20], [4075:4095]};
}
Efficient constraint
rand bit [31:0] addr;
constraint c {
addr [11:0] inside {[0:20], [4075:4095]};
}
130
Iterative and Array Constraints

Array Size
The easiest array constraint to understand is the size
function.
Example:
class dyn_size;
rand bit [31:0] d[];
constraint d_size {d.size() inside
{[1:10]};}
endclass: dyn_size
131
Iterative and Array Constraints (cont)

Sum of Elements
Example:
class sum_arr;
rand bit v [10];
constraint v_sum {v.sum()==4h4;}
endclass: sum_arr
132

Issues with Array Constraints
Example:
class bad_sum;
rand byte len [];
constraint c_len {len.sum() < 1024;
len.size() inside {[1:8]};}
function void display();
$write(sum=%d val=, len.sum());
foreach(len[i])
$write(%d, len[i]);
$display;
endfunction: display
endclass: bad_sum
133

Issues with Array Constraints (cont)
#
#
#
#
#
sum
sum
sum
sum
sum
=-120,val=-120
= 50,val= 123 53 60
= 80,val= 80
=
5,val=-113 26 87
= 13,val=-111-123 -87
59
11
5
78
Drawback: the sum is somtime negative and is

always less than 127
134

Issues with Array Constraints (cont)
class good_sum;
rand uint len[];
constraint c_len {
foreach(len[i])
len inside {[1:255]};
len.sum() <1024;
len.size() inside {[1:8]};}
endclass
135

Generating an Array of Unique Values
Using randc to create unique random values in a
range 0:max-1
Example:
class randcrange;
randc bit [15:0] value;
int max_value;
function new (input int max_value=10)
this.value=value;
endfunction
constraint c_max_value {value<max_value;}
endclass: randcrange
136
Random control
Introduction to randcase
You can use randcase tomake a weighted choice between
several actions, without having to create a class and
instance
Example:
initial begin
bit [15:0] len;
randcase
1: len=$urandom_range(0,2); //10%: 0,1,2
8: len=$urandom_range(3,5); //80%: 3,4,5
1: len=$urandom_range(6,7); //10%: 6,7
endcase
end
137
Random Number Generators

Pseudorandom Number Generators
Verilog uses a simple PRNG that you could access with
the $random function
Simple pseudorandom number generator
bit [31:0] state = 32h12345678;
function bit [31:0] my_random();
bit [63:0] s64;
s64 = state * state;
state = (s64 >> 16) + state;
return state;
endfunction
138

Random Stability
In Verilog, if the source code does not change ,with
the same seed, the simulator producess the same
random stimulus on any mechine or any operating
system and we miss the bug.
139

Random Stability (cont)
Example:
module random_v ;
initial
repeat(5)
$display (random = %d, $random(2));
endmodule: random_v
#
#
#
#
#
random
random
random
random
random
=
=
=
=
=
-2147345408
-2147345408
-2147345408
-2147345408
-2147345408
140

In SystemVerilog seeding will be done hierachily.
Every module instance, interface instance, program
instance and package has initialization PRNG. Every
thread and object has independent PRNG . When
ever dynamic thread is created its PRNG is initialized
with the next random value from its parent thread.
141

Example:
class Ran_1;
module Ran_Stb;
rand bit [2:0] Var; Ran_1 r1 = new();
endclass
Ran_2 r2 = new();
initial
class Ran_2;
begin
rand bit [2:0] Var; repeat(5) begin
endclass
void'(r1.randomize());
$display("Ran_1.Var : %0d ", r1.Var);
end
repeat(5) begin
end
end
endmodule
142

Result:
#
#
#
#
#
#
#
#
#
#
Ran_1.Var
Ran_1.Var
Ran_1.Var
Ran_1.Var
Ran_1.Var
Ran_2.Var
Ran_2.Var
Ran_2.Var
Ran_2.Var
Ran_2.Var
:
:
:
:
:
:
:
:
:
:
0
5
0
3
4
5
5
1
7
1
143

Example:
class Ran_1;
module Ran_Stb;
rand bit [2:0] Var; Ran_1 r1 = new();
endclass
Ran_2 r2 = new();
initial
class Ran_2;
begin
rand bit [2:0] Var; repeat(5) begin
endclass
end
repeat(5) begin
end
end
endmodule
144

Result:
#
#
#
#
#
#
#
#
#
#
Ran_2.Var
Ran_2.Var
Ran_2.Var
Ran_2.Var
Ran_2.Var
Ran_1.Var
Ran_1.Var
Ran_1.Var
Ran_1.Var
Ran_1.Var
:
:
:
:
:
:
:
:
:
:
5
5
1
7
1
0
5
0
3
4
145

Sometimes it is desirable to manually seed an
objects RNG using the srandom()method.
146

Example:
class Rand_seed;
module Rand_seed;
rand integer Var;
Rand_seed rs;
function new (int seed);
initial
srandom(seed);
begin
$display(" SEED is initised to rs = new(20);
%0d ",seed);
repeat(5)
endfunction
void'(rs.randomize());
rs = new(1);
function void
repeat(5)
post_randomize();
void'(rs.randomize());
$display(": %0d :",Var);
end
endfunction
endmodule
endclass
147

Result:
#
#
#
#
#
#
#
#
#
#
#
#
SEED is initised to 20
: 1189201676 :
: -50602121 :
: 1441010736 :
: 999569011 :
: -161019490 :
SEED is initised to 1
: 1232952047 :
: 9295156 :
: -183300904 :
: -83119859 :
: 1832521658 :
148
Thread and Inter-process

Communication
7/16/15
Content
Working with threads

Events
Mailboxes
Semaphore
Building a test bench with threads
150
Thread and IPC

Overview
Thread: To stimulate and check blocks (initial, always,)

All running in parallel and run in their own thread
Scheduler chooses which thread runs next
IPC: To communicate with other threads
Methods:
- Event
- Mailbox
- Semaphore
151
Working With Threads

forkjoin
Statements in a forkjoin execute in parallel
All inside statements have to finish before the rest of the
block can continue => limmited
New ways to create threads:
- forkjoin_none
- forkjoin_any
152

Using forkjoin and beginend
153

forkjoin_none (Spawning Threads)
- Schedules
each
statement in
the block
- Execution
continues in
the parent
thread
154

forkjoin_any (Synchronizing Thread)
- Schedules
each statement
in the block.
- Complete first
statement.
- Then, execute
continue in the
parent thread.
155

Creating Threads in a Class
The run task starts a
thread in a fork
join_none block
- Do not start any
threads in new()
function
156
Disabling Threads
Disabling a Single Thread
- Labelling for
the blocks to
specify what
to stop.
- Use disable
function.
157
Disabling Threads
Disabling Multiple Thread
- Use disable
fork function.
- Stop threads
2,3,4
158
IPC Events
A handle to a synchronization object that can be
passed around to routines
To share events across objects without having to make
the events global
The most common way is to pass the event into the
constructor for an object
Operator:
@ a thread waits for an event to change
-> unblocking the first thread
Status e.triggered check whether an event has been
triggered
159
IPC Events
Blocking on the Edge of an Event
- One initial block starts, triggers its event, and then

blocks on the other event
- The second thread locks up because it missed the
first event, as it is a zerowidth pulse
160
IPC Events
Waiting for an Event Trigger
- One initial block starts, triggers its event, and then

blocks on the other event
- The second block starts, triggers its event (waking
up the first) and then blocks on the first event
161
IPC Events
Passing
Events
162
IPC Semaphores
Semaphore: to control access to a resource using
a key
semaphore sem; //create a semaphore
Tasks
new(num_key) create a semaphore with one or
more keys
get() get one or more
put() return one or more keys
try_get() try to get a semaphore, obtains
available keys and returns 1. returns 0 if there are
not sufficient keys
163
IPC Semaphores
Example
164
IPC Mailboxs
Mailbox: To pass information between two threads
mailbox #(obj_type) mbx; //create a

parameterized mailbox
Tasks
put() put data into a mailbox
get() remove data
try_put() to see if the mailbox is full.
try_get() to see if it is empty.
peek() gets a copy of the data in the mailbox but does not
remove it
165
IPC Mailboxs
Mailbox in a Testbench
166
Building a Testbench with Threads and IPC

Layered testbench with environment
167

Example
168

Example
169
Advanced OOP
Advanced OOP
Introduction to inheritance
o
Inheritance is the mechanism which allows a class A
to inherit properties of a class B.
o
A inherits from class B, then B is called superclass of
A, A is called subclass of B.
171
Advanced OOP
Example
class Transaction;
rand bit [31:0] src,dst,data[8];
bit [31:0] csm;
virtual function void calc_csm();
csm = src^dst^data.xor;
endfunction
virtual function void display(input
string prefix="");
$display("%sTr: src = %h, dst=
%h, csm=%h, data=%p",
prefix,src,dst,csm,data) ;
endfunction
endclass
class BadTr extends Transaction;

rand bit bad_csm;
virtual function void calc_csm();
super.calc_csm();
if (bad_csm) csm = ~csm;
endfunction
virtual function void
display(input string prefix="");
$write("%sBadTr: bad_csm=%b,
" , prefix, bad_csm);
super.display();
endfunction
endclass
172
Advanced OOP
A subclass inherits all the members (fields, methods,
and nested classes) from its superclass. But constructor
not inherited by subclasses.
Example:
173
Advanced OOP
Downcasting and Virtual Methods
Downcasting is the act of casting a base class handle
to point to an object that is a class extended from that
base type.
174
Advanced OOP
Example:
175
Advanced OOP
SystemVerilog provides the $cast system task to assign
values to variables that might not ordinarily be valid
because of differing data type.
The syntax for $cast() is as follows:
task $cast( singular dest_handle, singular source_handle );
function int $cast(singular dest_handle, singular source_handle );
176
Advanced OOP
Example:
177
THANK FOR WATCHING!
178

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Verification Training

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Methodology, Data types,

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Functional verification need

Self-checking test bench

Does a design work and how is it done?

Coverage driven constraint random verification

Verification plan and phases of verification

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Functional verification need

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Self-checking test bench

Code coverage (Cont)

Code coverage (Cont)

Coverage driven constraint random

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Coverage driven constraint random

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Verification Plan Contains The Following:

4-state and 2-state data types

2 state data type: (0,1)

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// Signed packed array

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User-defined data types with typedef

Create new types using the typedef statement

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User-defined data structure

Initializing a Structure: using `{value1, value2};

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Procedural Statements and Routines

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Procedural Statements and Routines

Procedural Statements and Routines

Basic Object Oriented

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Defining Methods Outside of the Class

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Static Variables vs. Global Variables

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Static Variables vs. Global Variables

Static Variables vs. Global Variables

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Using One Class Inside Another